• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.7
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.9
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• pp.1010-1019
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• 2016

The K-user multiple-input single-output broadcast channel is considered under per-antenna power constraints, i. e., each transmit antenna must satisfy its own power constraints. A low complexity zeroforcing(ZF) precoder is proposed when the number of transmit antennas M is greater than K. The proposed precoder design significantly reduces computational complexity for the precoder construction while attaining the sum spectral efficiency close to that achievable by the optimal ZF precoder.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.4
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• pp.1042-1058
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• 2024

Terahertz (THz) communication is becoming a key technology for future 6G wireless networks because of its ultra-wide band. However, the implementation of THz communication systems confronts formidable challenges, notably beam splitting effects and high computational complexity associated with them. Our primary objective is to design a hybrid precoder that minimizes the Euclidean distance from the fully digital precoder. The analog precoding part adopts the delay-phase alternating minimization (DP-AltMin) algorithm, which divides the analog precoder into phase shifters and time delayers. This effectively addresses the beam splitting effects within THz communication by incorporating time delays. The traditional digital precoding solution, however, needs matrix inversion in THz massive multiple-input multiple-output (MIMO) communication systems, resulting in significant computational complexity and complicating the design of the analog precoder. To address this issue, we exploit the characteristics of THz massive MIMO communication systems and construct the digital precoder as a product of scale factors and semi-unitary matrices. We utilize Schatten norm and Hölder's inequality to create semi-unitary matrices after initializing the scale factors depending on the power allocation. Finally, the analog precoder and digital precoder are alternately optimized to obtain the ultimate hybrid precoding scheme. Extensive numerical simulations have demonstrated that our proposed algorithm outperforms existing methods in mitigating the beam splitting issue, improving system performance, and exhibiting lower complexity. Furthermore, our approach exhibits a more favorable alignment with practical application requirements, underlying its practicality and efficiency.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.112-118
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• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• The Magazine of the IEIE
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• v.25 no.5
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• ETRI Journal
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• v.39 no.3
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• pp.326-335
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• 2017

In the uplink transmission of massive (or large-scale) multi-input multi-output (MIMO) systems, large dimensional signal detection and its hardware design are challenging issues owing to the high computational complexity. In this paper, we propose low-complexity hardware architectures of Richardson iterative method-based massive MIMO detectors. We present two types of massive MIMO detectors, directly mapped (type1) and reformulated (type2) Richardson iterative methods. In the proposed Richardson method (type2), the matrix-by-matrix multiplications are reformulated to matrix-vector multiplications, thus reducing the computational complexity from $O(U^2)$ to O(U). Both massive MIMO detectors are implemented using a 65 nm CMOS process and compared in terms of detection performance under different channel conditions (high-mobility and flat fading channels). The hardware implementation results confirm that the proposed type1 Richardson method-based detector demonstrates up to 50% power savings over the proposed type2 detector under a flat fading channel. The type2 detector indicates a 37% power savings compared to the type1 under a high-mobility channel.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.6
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• pp.2908-2924
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• 2019

Multiple input multiple output orthogonal frequency division multiplexing (MIMO-OFDM) is widely applied in wireless communication by virtue of its excellent properties in data transmission rate and transmission accuracy. However, as a major drawback of MIMO-OFDM systems, the high peak-to-average power ratio (PAPR) complicates the design of the power amplifier at the receiver end. Some available PAPR reduction methods such as selective mapping (SLM) suffer from high computational complexity. In this paper, a low-complexity SLM method based on active constellation extension (ACE) and joint space-time selective mapping (AST-SLM) for reducing PAPR in Alamouti STBC MIMO-OFDM systems is proposed. In SLM scheme, two IFFT operations are required for obtaining each transmission sequence pair, and the selected phase vector is transmitted as side information(SI). However, in the proposed AST-SLM method, only a few IFFT operations are required for generating all the transmission sequence pairs. The complexity of AST-SLM is at least 86% less than SLM. In addition, the SI needed in AST-SLM is at least 92.1% less than SLM by using the presented blind detection scheme to estimate SI. We show, analytically and with simulations, that AST-SLM can achieve significant performance of PAPR reduction and close performance of bit error rate (BER) compared to SLM scheme.

• International Journal of Aeronautical and Space Sciences
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• v.17 no.1
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• pp.29-36
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• 2016

Tensairity girder is a light weight inflatable fabric structural concept which can be used in road emergency transportation. It uses low pressure air to stabilize compression elements against buckling. With the purpose of obtaining the comprehensive target of minimum deflection and weight under ultimate load, the cross-section and the inner pressure of tensairity girder was optimized in this paper. The Variable Complexity Modeling (VCM) method was used in this paper combining the Kriging approximate method with the Finite Element Analysis (FEA) method, which was implemented by ABAQUS. In the Kriging method, the sample points of the surrogate model were outlined by Design of Experiment (DOE) technique based on Optimal Latin Hypercube. The optimization framework was constructed in iSIGHT with a global optimization method, Multi-Island Genetic Algorithm (MIGA), followed by a local optimization method, Sequential Quadratic Program (SQP). The result of the optimization gives a prominent conceptual design of the tensairity girder, which approves the solution architecture of VCM is feasible and efficient. Furthermore, a useful trend of sensitivity between optimization variables and responses was performed to guide future design. It was proved that the inner pressure is the key parameter to balance the maximum Von Mises stress and deflection on tensairity girder, and the parameters of cross section impact the mass of tensairity girder obviously.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.227-233
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• 2016

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for $GF(2^m)$ fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.