• Title/Summary/Keyword: low-complexity design

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Measurement of Noise Parameters Using 6-Port Network (Invited Paper) (6-포트 회로망을 이용한 잡음 파라미터 측정)

  • Yeom, Kyung-Whan;Ahmed, Abdule-Rahman
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.2
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    • pp.119-126
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    • 2015
  • The information about noise parameters is essential in the design of low noise amplifier. In the past, the noise parameters were measured using an impedance tuner and noise figure analyzer. Recently, the authors proposed the method of measuring the noise parameters using the 8-port network without the aid of the mechanically driven impedance tuner. However, the 8-port method still requires the noise source and causes the complexity in the measurements. In this paper, a novel measurement method of the noise parameters without the noise source using 6-port network is proposed. Based on the proposed 6-port method, the noise parameters of 10 dB attenuator whose noise parameters can be theoretically determined were measured and the measured noise parameters are compared with those measured using the previous 8-port network method. As a result, the accuracy of the measured noise parameters using 6-port network is found to be comparable to the previous 8-port network method.

Design of Time Synchronizer for Advanced LR-WPAN Systems (개선된 LR-WPAN 시스템을 위한 시간 동기부 설계)

  • Park, Mincheol;Lee, Dongchan;Jang, Soohyun;Jung, Yunho
    • Journal of Advanced Navigation Technology
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    • v.18 no.5
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    • pp.476-482
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    • 2014
  • Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. IEEE 802.15.4 LR-WPAN system using 2.45 GHz frequency band is very popular for the sensor applications. However, since LR-WPAN only supports the data rate of 250 kbps, it has a limit to be applied to various sensor networks. Therefore, we define the preamble structure which can support the data rates of 31.25 kbps, 62.5 kbps, 125 kbps, and present the low-complexity hardware architecture for time synchronizer based on double-correlation algorithm which can resist the CFO (carrier frequency offset). Implementation results show that the proposed time synchronizer include the logic slice of 18.36 K and four DSP48s, which are reduced at the rate of 79.1% and 99.4%, respectively, compared with existing architecture.

Optimized Sigma-Delta Modulation Methodology for an Effective FM Waveform Generation in the Ultrasound System (효율적인 주파수 변조된 초음파 파형 발생을 위한 최적화된 시그마 델타 변조 기법)

  • Kim, Hak-Hyun;Han, Ho-San;Song, Tai-Kyong
    • Journal of Biomedical Engineering Research
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    • v.28 no.3
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    • pp.429-440
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    • 2007
  • A coded excitation has been studied to improve the performance for ultrasound imaging in term of SNR, imaging frame rate, contrast to tissue ratio, and so forth. However, it requires a complicated arbitrary waveform transmitter for each active channel that is typically composed of a multi-bit Digital-to-Analog Converter (DAC) and a linear power amplifier (LPA). Not only does the LPA increase the cost and size of a transmitter block, but it consumes much power, increasing the system complexity further and causing a heating-up problem. This paper proposes an optimized 1.5bit fourth order sigma-delta modulation technique applicable to design an efficient arbitrary waveform generator with greatly reduced power dissipation and hardware. The proposed SDM can provide a required SQNR with a low over-sampling ratio of 4. To this end, the loop coefficients are optimized to minimize the quantization noise power in signal band while maintaining system stability. In addition, the decision level for the 1.5 bit quantizer is optimized for a given input waveform, which results in the SQNR improvement of more than 5dB. Computer simulation results show that the SQNR of a FM(frequency modulated) signal generated by using the proposed method is about 26dB, and the peak side-lobe level (PSL) of its compressed waveform on receive is -48dB.

A Design of High Performance Motion Estimation Hardware for H.264/AVC (H.264/AVC를 위한 고성능 움직임 예측 하드웨어 설계)

  • Park, Seungyong;Ryoo, Kwangki
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.1
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    • pp.124-130
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    • 2013
  • In this paper, a new motion estimation algorithm with low-computational complexity is proposed to improve the performance of H.264/AVC. The proposed architecture uses the directions of the median motion vector which is computed by the motion vectors of the three neighbor macroblocks in Integer Motion Estimation. By using the directions of the vector, the proposed architecture has a single computational level instead of multi-computational levels in Integer Motion Estimation. The proposed motion estimation is synthesized using the TSMC 0.18um standard cell library. The synthesis result shows that the gate count is about 217.92K at 166MHz and it was improved about 69% compared with previous one.

Human-Induced Vibrations in Buildings

  • Wesolowsky, Michael J.;Irwin, Peter A.;Galsworthy, Jon K.;Bell, Andrew K.
    • International Journal of High-Rise Buildings
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    • v.1 no.1
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    • pp.15-19
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    • 2012
  • Occupant footfalls are often the most critical source of floor vibration on upper floors of buildings. Floor motions can degrade the performance of imaging equipment, disrupt sensitive research equipment, and cause discomfort for the occupants. It is essential that low-vibration environments be provided for functionality of sensitive spaces on floors above grade. This requires a sufficiently stiff and massive floor structure that effectively resists the forces exerted from user traffic. Over the past 25 years, generic vibration limits have been developed, which provide frequency dependent sensitivities for wide classes of equipment, and are used extensively in lab design for healthcare and research facilities. The same basis for these curves can be used to quantify acceptable limits of vibration for human comfort, depending on the intended occupancy of the space. When available, manufacturer's vibration criteria for sensitive equipment are expressed in units of acceleration, velocity or displacement and can be specified as zero-to-peak, peak-to-peak, or root-mean-square (rms) with varying frequency ranges and resolutions. Several approaches to prediction of floor vibrations are currently applied in practice. Each method is traceable to fundamental structural dynamics, differing only in the level of complexity assumed for the system response, and the required information for use as model inputs. Three commonly used models are described, as well as key features they possess that make them attractive to use for various applications. A case study is presented of a tall building which has fitness areas on two of the upper floors. The analysis predicted that the motions experienced would be within the given criteria, but showed that if the floor had been more flexible, the potential exists for a locked-in resonance response which could have been felt over large portions of the building.

Adaptive Switching Equalization for SC-FDMA System (SC-FDMA 시스템을 위한 적응형 스위칭 등화기법)

  • Kim, Joo-Chan;Bae, Jung-Nam;Kim, Jin-Young
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.9 no.6
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    • pp.23-28
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    • 2009
  • In this paper, we proposed and analyzed the performance of the adaptive switching equalization for SC-FDMA system. It is well known that SC-FDMA system have a fairly similar structure to OFDMA system. Furthermore, SC-FDMA system has great advantage of low PAPR compare to OFDM system. However, this system often suffers from wireless channel characteristics such as multipath fading and increased channel impulse response and so on. To reduce this channel influence, it strongly requires efficient adaptive equalization. Therefore, the proposed system operated upon two modes namely, ZF mode for slow speed and MMSE mode for high speed. From the simulation results, we can confirm that the proposed scheme has more efficient performance from the system complexity point of view. So we can expect that the proposed system will be applied design of 3GPP LTE uplink.

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Designing Distributed Real-Time Systems with Decomposition of End-to-End Timing Donstraints (양극단 지연시간의 분할을 이용한 분산 실시간 시스템의 설계)

  • Hong, Seong-Soo
    • Journal of Institute of Control, Robotics and Systems
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    • v.3 no.5
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    • pp.542-554
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    • 1997
  • In this paper, we present a resource conscious approach to designing distributed real-time systems as an extension of our original approach [8][9] which was limited to single processor systems. Starting from a given task graph and a set of end-to-end constraints, we automatically generate task attributes (e.g., periods and deadlines) such that (i) the task set is schedulable, and (ii) the end-to-end timing constraints are satisfied. The method works by first transforming the end-to-end timing constraints into a set of intermediate constraints on task attributes, and then solving the intermediate constraints. The complexity of constraint solving is tackled by reducing the problem into relatively tractable parts, and then solving each sub-problem using heuristics to enhance schedulability. In this paper, we build on our single processor solution and show how it can be extended for distributed systems. The extension to distributed systems reveals many interesting sub-problems, solutions to which are presented in this paper. The main challenges arise from end-to-end propagation delay constraints, and therefore this paper focuses on our solutions for such constraints. We begin with extending our communication scheme to provide tight delay bounds across a network, while hiding the low-level details of network communication. We also develop an algorithm to decompose end-to-end bounds into local bounds on each processor of making extensive use of relative load on each processor. This results in significant decoupling of constraints on each processor, without losing its capability to find a schedulable solution. Finally, we show, how each of these parts fit into our overall methodology, using our previous results for single processor systems.

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Preservice Secondary Mathematics Teachers' Statistical Literacy in Understanding of Sample (중등수학 예비교사들의 통계적 소양 : 표본 개념에 대한 이해를 중심으로)

  • Tak, Byungjoo;Ku, Na-Young;Kang, Hyun-Young;Lee, Kyeong-Hwa
    • The Mathematical Education
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    • v.56 no.1
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    • pp.19-39
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    • 2017
  • Taking samples of data and using samples to make inferences about unknown populations are at the core of statistical investigations. So, an understanding of the nature of sample as statistical thinking is involved in the area of statistical literacy, since the process of a statistical investigation can turn out to be totally useless if we don't appreciate the part sampling plays. However, the conception of sampling is a scheme of interrelated ideas entailing many statistical notions such as repeatability, representativeness, randomness, variability, and distribution. This complexity makes many people, teachers as well as students, reason about statistical inference relying on their incorrect intuitions without understanding sample comprehensively. Some research investigated how the concept of a sample is understood by not only students but also teachers or preservice teachers, but we want to identify preservice secondary mathematics teachers' understanding of sample as the statistical literacy by a qualitative analysis. We designed four items which asked preservice teachers to write their understanding for sampling tasks including representativeness and variability. Then, we categorized the similar responses and compared these categories with Watson's statistical literacy hierarchy. As a result, many preservice teachers turned out to be lie in the low level of statistical literacy as they ignore contexts and critical thinking, expecially about sampling variability rather than sample representativeness. Moreover, the experience of taking statistics courses in university did not seem to make a contribution to development of their statistical literacy. These findings should be considered when design preservice teacher education program to promote statistics education.

A Design and Implementation Digital Vessel Bio Emotion Recognition LED Control System (디지털 선박 생체 감성 인식 LED 조명 제어 시스템 설계 및 구현)

  • Song, Byoung-Ho;Oh, Il-Whan;Lee, Seong-Ro
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.48 no.2
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    • pp.102-108
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    • 2011
  • The existing vessels lighting control system has several problems, which are complexity of construction and high cost of establishment and maintenance. In this paper, We designed low cost and high performance lighting control system at digital vessel environment. We proposed a system which recognize the user's emotions after obtaining the biological informations about user's bio information(pulse sensor, blood pressure sensor, blood sugar sensor etc) through wireless sensors controls the LED Lights. This system classified emotions using backpropagation algorithm. We chose 3,000 data sets to train the backpropagation algorithm. As a result, obtained about 88.7% accuracy. And the classified emotions find the most appropriate point in the method of controlling the waves or frequencies to the red, green, blue LED Lamp comparing with the 20-color-emotion models in the HP's 'The meaning of color' and control the brightness or contrast of the LED Lamp. In this method, the system saved about 20% of the electricity consumed.

Fast Fourier Transform Processor based on Low-power and Area-efficient Algorithm (저 전력 및 면적 효율적인 알고리즘 기반 고속 퓨리어 변환 프로세서)

  • Oh Jung-yeol;Lim Myoung-seob
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.42 no.2 s.302
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    • pp.143-150
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    • 2005
  • This paper proposes a new $radix-2^4$ FFT algorithm and an efficient pipeline architecture based on this new algorithm for OFDM systems. The pipeline architecture based on the new algorithm has the same number of multipliers as that of the $radix-2^2$ algorithm. However, the multiplier complexity could be reduced by more than $30\%$ by replacing one half of the programmable complex multipliers by the newly proposed CSD constant complex multipliers. From synthesis simulations of a standard 0.35um CMOS Samsung process, a proposed CSD constant complex multiplier achieved more than $60\%$ area efficiency when compared with the conventional programmable complex multiplier. This promoted efficiency can be used for the design of a long length FFT processor in wireless OFDM applications which needs more power and area efficiency.