• ETRI Journal
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• 제35권2호
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• pp.336-339
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• 2013

To enhance the symbol error rate (SER) performance of the two-way relay channels with physical layer network coding, this letter proposes a relay selection scheme, in which the relay with the maximal minimum distance between different points in its constellation among all relays is selected to assist two-way transmissions. We give the closed-form expression of minimum distance for binary phase-shift keying and quadrature phase-shift keying. Additionally, we design a low-complexity method for higher-order modulations based on look-up tables. Simulation results show that the proposed scheme improves the SER performance for two-way relay networks.

• 한국정보처리학회논문지
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• 제1권4호
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• pp.438-451
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• 1994

프로그램 가능한 논리제어기(PLC : Programmable Logic Controller)의 활용을 위 한 낮은 복잡성과 결함탐색 기능을 갖는 컴퓨터 구조를 설계하였다. PLC의 반복적인 운영모드와 명세단계, 응용분야에 따라 표준화한 소프트웨어 기능모듈들의 상호연결 을 기본으로 하는 그래픽 프로그래밍 패러다임(paradigm)이 구조적으로 지원된다. 그러므로 설계과정에서 프로그래밍 단계와 가장 단순하면서도 엄격한 Diverse Back Translation 방법에 의해 응용소프트웨어의 안전성 인증을 가능케하는 컴퓨터 실행 (machine execution) 단계 사이의 의미상 격차(semantic gap)가 제거된다.

• 산업경영시스템학회지
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• 제21권45호
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• pp.319-328
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• 1998

In this paper, the design of ALT(Accelerated Life Test) requires a sampling plan based on failure-censored(Type II censored) ALT with lognormal life distribution. Specially the environmental effect of products has been emphasized, so we considered the upper life limit as well as lower life limit in the ALT sampling plan. The optimal plan with a high stress and a low stress is used as test plan, and the total sample size for test and lot acceptability constant which minimize an asymptotic variance of maximum likelihood estimator of assumed model parameters and satisfy the given producer's risk and customer's risk are drawn out. These values can be acquired by means of the computer program that we coded for resolving the difficulty and complexity of calculation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 B
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• pp.348-351
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• 2000

There have been significant advances in thyratron performance in recent years. these advanced waveforms have increased the complexity and cost of drive circuits. Thyratrons can reliably switch anode voltages up to 40kV and conduct peak currents up to 10kA or more. So stable thyratron drivers are essential for reliable high voltage pulse modulators. In order to operate thyratron well, thyratron driver need high repetition rate, fast rising time and low jitter. In this paper, used power MOSFET/transformer combinations. Designed thyratron driver is satisfied requirements and experimental results are presented to confirm.

• 센서학회지
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• 제24권2호
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• pp.107-112
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeys simultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate the keys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processes to minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times compared to the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two times compared to the conventional counterpart.

• Journal of Power Electronics
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• 제10권4호
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• pp.365-373
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• 2010

This paper proposes a hybrid single carrier sinusoidal modulation suitable for multiphase multilevel inverters. Multiphase multilevel inverters are controlled by hybrid modulation to provide multiphase variable voltage and a variable frequency supply. The proposed modulation combines the benefits of fundamental frequency modulation and single carrier sinusoidal modulation (SC-SPWM) strategies. The main characteristics of hybrid modulation are a reduction in switching losses and improved harmonic performance. The proposed algorithm can be applied to cascaded multilevel inverter topologies. It has low computational complexity and it is suitable for hardware implementations. SC-SPWM and its base modulation design are implemented on a TMS320F2407 digital signal processor (DSP). A Complex Programmable Logic Device realizes the hybrid PWM algorithm and it is integrated with a DSP processor for hybrid SC-SPWM generation. The feasibility of this hybrid modulation is verified by spectral analysis, power loss analysis, simulation and experimental results.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제17권1호
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• pp.202-215
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• 2023

This paper proposes a non-orthogonal multiple access (NOMA) based low-complexity relaying approach for multiuser cellular two-way relay channels (CTWRCs). In the proposed scheme, the relay detects the signal using successive interference cancellation (SIC) and re-generates the transmit signal with zero-forcing (ZF) transmit precoding. The achievable data rates of the NOMA-based multiuser two-way relaying (TWR) approach is analyzed. We further study the power allocation among different data streams to maximize the weighted sum-rate (WSR). We re-form the resultant non-convex problem into a standard monotonic program. Then, we design a polyblock outer approximation algorithm to sovle the WSR problem.The proposed optimal power allocation algorithm converges fast and it is shown that the NOMA-TWR-OPA scheme outperforms a NOMA benchmark scheme and conventional TWR schemes.

• Structural Engineering and Mechanics
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• 제91권4호
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• pp.403-416
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• 2024

The single-column pier girder bridge, due to its low engineering cost, small footprint, and aesthetic appearance, is extensively employed in urban viaducts and interchange ramps. However, its structural design makes it susceptible to eccentric loads, flexural-torsional coupling effects, and centrifugal forces, among others. To evaluate its anti-overturning performance reasonably, it is crucial to determine the reaction force of the support for the single-column pier girder bridge. However, due to the interaction between vehicle and bridge and the complexity of vibration modes, it poses a significant challenge to analyze the theory or finite element method of single-column pier girder bridges. The unit load bearing reaction coefficient method is proposed in this study to facilitate the static analysis. Numerous parameter analyses have been conducted to account for the dynamic amplification effect. The results of these analyses reveal that the dynamic amplification factor is independent of road surface roughness but is influenced by factors such as the position of the support. Based on parameter analysis, the formula of the dynamic amplification factor is derived by fitting.

• 한국항행학회논문지
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• 제23권2호
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• pp.207-213
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• 2019

최근 IoT 산업에서 보안의 중요성이 증가하고 있으며, IoT (internet of things) 통신 산업에서는 소형의 하드웨어 칩이 필요하다. 이를 위해 본 논문에서는 대표적인 블록 암호 알고리즘인 AES (advanced encryption standard), ARIA (academy, research, institute, agency)와 CLEFIA를 통합한 저면적 암호화 프로세서를 제안한다. 제안하는 암호화 프로세서는 128 비트 기반으로 라운드 키 생성 과정과 암호화 및 복호화 과정을 하나로 공유하였으며, 각각 알고리즘의 구조를 공유 시켜 면적을 축소하였다. 더불어, 경량 IoT 기기를 포함한 대부분의 IoT 기기나 시스템에 적용이 가능하도록 구현하였다. 본 프로세서는 Verilog HDL (hardware description language)로 기술되었고65nm CMOS 공정을 통해 논리 합성하여 11,080개의 논리 게이트로 구현 가능함을 확인하였다. 결과적으로 각 알고리즘 개별 구현 대비 gate 수 총계에서 약42%의 이점을 보인다.

• 정보처리학회논문지A
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• 제8A권4호
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• pp.479-488
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• 2001

SoC 설계의 복잡도가 지속적으로 커짐에 따라 기존의 소프트웨어 모델을 이용한 시뮬레이션 방법으로는 이를 검증하기에는 너무 많은 시간이 소요되어 많은 문제가 있다. 이를 해결하기 위해 시뮬레이션 방법보다 훨씬 빠른 검증속도를 제공하는 다양한 FPGA 기반의 로직 에뮬레이터가 활발히 연구되어왔다. 하지만 제한된 FPGA 핀 수로 인해 FPGA 내부에서 매우 낮은 자원이용률을 초래하고 있을 뿐만 아니라, 검증 대상이 되는 회로의 크기가 커짐에 비례하여 에뮬에이션의 속도가 현저하게 느려지는 문제점이 있다. 본 논문에서는 파이프라인 방식의 신호전달을 통하에 FPGA의 자원이용률을 극대화할 수 있을 뿐만 아니라 에뮬레이션의 속도도 크게 높일 수 있는 시스템 수준의 새로운 에뮬레이터 구조와 소프트웨어를 제안한다. 파이프라인의 링을 통하여 다수의 로직신호선을 하나의 실제 핀에 할당하여 핀 제한 문제를 해결하고, FPGA 간의 신호전달 경로를 사용자회로와 분리시킴으로서 빠른 시스템 클록의 사용을 가능케 하며 분할된 회로간에 조합경로를 줄여 실제 에뮬레이션클록의 속도를 높일 수 있었다. 또한 신호의 전달을 파이프라인 방식으로 보내기 위해 적용하는 스케줄링을 계산의 복잡도가 낮은 휴리스틱 방법을 적용하였다. 12비트 마이크로콘트롤로를 간단한 휴리스틱 스케줄링 알고리즘을 적용한 실험결과를 통하여 높은 검증속도를 확인하였다.