• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2232-2235
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• 2003

In speech communication systems where two different speech codecs are interoperated, transcoding algorithm is a good approach because of its low complexity and improved synthesized speech quality. This paper proposes an efficient method to further improve the performance of transcoding algorithms as well as to reduce the complexity. In the conventional transcoding algorithms. a post-filter and a perceptual weighting filter should be operated sequentially because both decoding and encoding processes are needed. This results in the redundancy of the processing in terms of complexity and perceptual quality. Using the fact that their filter structures are similar, we replaced the two filters with one. The proposed algorithm requires 72.8% lower complexity than the conventional transcoding algorithm when we compare only the complexity of the filtering processes. The results of both objective and subjective tests verify that the proposed algorithm has slightly better quality than the conventional one.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.11
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• pp.4573-4584
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• 2015

The traditional feature extraction algorithms for recognition of communication signals can hardly realize the balance between computational complexity and signals' interclass gathered degrees. They can hardly achieve high recognition rate at low SNR conditions. To solve this problem, a novel feature extraction algorithm based on Holder coefficient was proposed, which has the advantages of low computational complexity and good interclass gathered degree even at low SNR conditions. In this research, the selection methods of parameters and distribution properties of the extracted features regarding Holder coefficient theory were firstly explored, and then interval gray relation algorithm with improved adaptive weight was adopted to verify the effectiveness of the extracted features. Compared with traditional algorithms, the proposed algorithm can more accurately recognize signals at low SNR conditions. Simulation results show that Holder coefficient based features are stable and have good interclass gathered degree, and interval gray relation classifier with adaptive weight can achieve the recognition rate up to 87% even at the SNR of -5dB.

• ETRI Journal
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• v.38 no.1
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• pp.62-69
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• 2016

In this paper, we propose two novel user selection algorithms for multiuser multiple-input and multiple-output downlink wireless systems, in which both a base station (BS) and mobile stations (MSs) are equipped with multiple antennas. Linear transmit beamforming at the BS and receive combining at the MSs are used to avoid interference between users and find a better sum-rate capacity performance. An optimal technique for selecting users would entail an exhaustive search, which in practice becomes computationally complex for a realistic number of users. Suboptimal algorithms with low complexity are proposed for a coordinated beamforming scheme. Simulation results show that the performance of the proposed algorithms is better than that provided by previous algorithms and is very close to an optimal approach with reduced complexity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• Journal of IKEEE
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• v.18 no.1
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• pp.165-171
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• 2014

This paper presents a low complexity QR decomposition (QRD) architecture for MIMO detector. In the proposed approach, various CORDIC-based QRD algorithms are efficiently combined together to reduce the computational complexity of the QRD hardware. Based on the computational complexity analysis on various QRD algorithms, a low complexity approach is selected at each stage of QRD process. The proposed QRD architecture can be applied to any arbitrary dimension of channel matrix, and the complexity reduction grows with the increasing matrix dimension. Our QR decomposition hardware was implemented using Samsung $0.13{\mu}m$ technology. The numerical results show that the proposed architecture achieves 47% increase in the QAR (QRD Rate/Gate count) with 28.1% power savings over the conventional Householder CORDIC-based architecture for the $4{\times}4$ matrix decomposition.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.801-805
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• 2006

A normalization approach to coefficient adaptation in the escalator(ESC) filter structure that conventionally employs least mean square(LMS) algorithm is introduced. Using Taylor's expansion of the local error signal, a normalized form of the ESC-LMS algorithm is derived. Compared with the computational complexity of the conventional ESC-LMS algorithm employs input power estimation for time-varying convergence coefficient using a single-pole low-pass filter, the computational complexity of the proposed method can be reduced by 50% without performance degradation.

• ETRI Journal
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• v.29 no.4
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• pp.445-451
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• 2007

An adaptive modulation scheme is presented for multiuser orthogonal frequency-division multiplexing systems. The aim of the scheme is to minimize the total transmit power with a constraint on the transmission rate for users, assuming knowledge of the instantaneous channel gains for all users using a combined bit-loading and subcarrier allocation algorithm. The subcarrier allocation algorithm identifies the appropriate assignment of subcarriers to the users, while the bit-loading algorithm determines the number of bits given to each subcarrier. The proposed bit-loading algorithm is derived from the geometric progression of the additional transmission power required by the subcarriers and the arithmetic-geometric means inequality. This algorithm has a simple procedure and low computational complexity. A heuristic approach is also used for the subcarrier allocation algorithm, providing a trade-off between complexity and performance. Numerical results demonstrate that the proposed algorithms provide comparable performance with existing algorithms with low computational cost.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.7
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Journal of Communications and Networks
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• v.13 no.3
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• pp.232-239
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• 2011

This paper investigates the user selection problem of successive zero-forcing precoded multiuser multiple-input multiple-output (MU-MIMO) downlink systems, in which the base station and mobile receivers are equipped with multiple antennas. Assuming full knowledge of the channel state information at the transmitter, dirty paper coding (DPC) is an optimal precoding strategy, but practical implementation is difficult because of its excessive complexity. As a suboptimal DPC solution, successive zero-forcing DPC (SZF-DPC) was recently proposed; it employs partial interference cancellation at the transmitter with dirty paper encoding. Because of a dimensionality constraint, the base station may select a subset of users to serve in order to maximize the total throughput. The exhaustive search algorithm is optimal; however, its computational complexity is prohibitive. In this paper, we develop two low-complexity user scheduling algorithms to maximize the sum rate capacity of MU-MIMO systems with SZF-DPC. Both algorithms add one user at a time. The first algorithm selects the user with the maximum product of the maximum column norm and maximum eigenvalue. The second algorithm selects the user with the maximum product of the minimum column norm and minimum eigenvalue. Simulation results demonstrate that the second algorithm achieves a performance similar to that of a previously proposed capacity-based selection algorithm at a high signal-to-noise (SNR), and the first algorithm achieves performance very similar to that of a capacity-based algorithm at a low SNR, but both do so with much lower complexity.