• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.205-215
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• 2007

This paper presents low latency and/or computation algorithms of iterative codes of turbo codes, turbo product codes and low density parity check codes for use in wireless broadband communication systems. Due to high coding complexity of iterative codes, this paper focus on lower complexity and/or latency algorithms that are easily implementable in hardware and further accelerate the decoding speed.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.7
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• pp.2998-3017
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• 2018

Massive (large-scale) MIMO (multiple-input multiple-output) is one of the key technologies in next-generation wireless communication systems. This paper proposes a high-performance low-complexity turbo receiver for SC-FDMA (single-carrier frequency-division multiple access) based MMIMO (massive MIMO) systems. Because SC-FDMA technology has the desirable characteristics of OFDMA (orthogonal frequency division multiple access) and the low PAPR (peak-to-average power ratio) of SC transmission schemes, the 3GPP LTE (long-term evolution) has adopted it as the uplink transmission to meet the demand high data rate and low error rate performance. The complexity of computing will be increased greatly in base station with massive MIMO (MMIMO) system. In this paper, a low-complexity adaptive turbo equalization receiver based on normalized minimal symbol-error-rate for MMIMO SC-FDMA system is proposed. The proposed receiver is with low complexity than that of the conventional turbo MMSE (minimum mean square error) equalizer and is also with better bit error rate (BER) performance than that of the conventional adaptive turbo MMSE equalizer. Simulation results confirm the effectiveness of the proposed scheme.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2633-2636
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• 2003

This study focuses on the new hardware design of fast and low-complexity multiplier over GF(2$\^$m/). The proposed multiplier based on the irreducible all one polynomial (AOP) of degree m, to reduced the system's complexity. It composed of Cyclic Shift, Partial Product, and Modular Summation Blocks. Also it consists of (m＋1)$^2$2-input AND gates and m(m＋1) 2-input XOR gates. Out architecture is very regular, modular and therefore, well-suited for VLSI implementation.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.298-300
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• 2004

In the decoding process of interframe wavelet coding, the inverse wavelet transform requires huge computational complexity. However, the decoder may need to be used in various devices such as PDAs, notebooks, PCs or set-top Boxes. Therefore, the decoder's complexity should be adapted to the processor's computational power. A decoder designed in accordance with the processor's computational power would provide optimal services for such devices. So, it is natural that the complexity scalability and the low complexity codec are also listed in the requirements for scalable video coding. In this contribution, we develop a method of controlling and lowering the complexity of the spatial wavelet transform while sustaining almost the same coding efficiency as the conventional spatial wavelet transform. In addition, the proposed method may alleviate the ringing effect for certain video data.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.5
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• pp.690-695
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• 2014

This paper presents a modified CCI image interpolation method based on the even-odd decomposition (EOD). The CCI method is a well-known technique to interpolate images. Although the method provides better image quality than the linear interpolation, its complexity still is a problem. To remedy the problem, this paper introduces analysis on the EOD decomposition of CCI and then proposes a reduced CCI interpolation in terms of complexity, providing better image quality in terms of PSNR. To evaluate the proposed method, we conduct experiments and complexity comparison. The results indicate that our method do not only outperforms the existing methods by up to 43% in terms of MSE but also requires low-complexity with 37% less computing time than the CCI method.

• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.1020-1026
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• 2016

Motion estimation (ME) algorithms supporting quarter-pixel accuracy have been recently introduced to retain detailed motion information for high quality of video in the state-of-the-art video compression standard of H.264/AVC. Conventional sub-pixel ME algorithms in the spatial domain are faced with a common problem of computational complexity because of embedded interpolation schemes. This paper proposes a low-complexity sub-pixel motion estimation algorithm in the transform domain utilizing shifting matrix. Simulations are performed to compare the performances of spatial-domain ME algorithms and transform-domain ME algorithms in terms of peak signal-to-noise ratio (PSNR) and the number of bits per frame. Simulation results confirm that the transform-domain approach not only improves the video quality and the compression efficiency, but also remarkably alleviates the computational complexity, compared to the spatial-domain approach.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.10
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• pp.5063-5073
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• 2016

In this paper, an efficient texture compression method is proposed for fast rendering, which exploits the spatial correlation among blocks through intra-picture block matching. Texture mapping is widely used to enhance the visual quality of results in real-time rendering applications. For fast texture mapping, it is necessary to identify an effective trade-off between compression efficiency and computational complexity. The conventional compression methods utilized for image processing (e.g., JPEG) provide high compression efficiency while resulting in high complexity. Thus, low complexity methods, such as ETC1, are often used in real-time rendering applications. Although these methods can achieve low complexity, the compression efficiency is still lower than that of JPEG. To solve this problem, we propose a texture compression method by reducing the spatial redundancy between blocks in order to achieve the better compression performance than ETC1 while maintaining complexity that is lower than that of JPEG. Experimental results show that the proposed method achieves better compression efficiency than ETC1, and the decoding time is significantly reduced compared to JPEG while similar to ETC1.

• Educational Technology International
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• v.25 no.1
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• pp.27-65
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• 2024

The purpose of this study was to identify differences in learning patterns according to content complexity in video-based learning environments and to derive variables that have an important effect on learning achievement within particular learning contexts. To achieve our aims, we observed and collected data on learners' cognitive processes through perceived affordances, using behavioral logs and eye movements as specific indicators. These two types of reaction data were collected from 67 male and female university students who watched two learning videos classified according to their task complexity through the video learning player. The results showed that when the content complexity level was low, learners tended to navigate using other learners' digital logs, but when it was high, students tended to control the learning process and directly generate their own logs. In addition, using derived prediction models according to the degree of content complexity level, we identified the important variables influencing learning achievement in the low content complexity group as those related to video playback and annotation. In comparison, in the high content complexity group, the important variables were related to active navigation of the learning video. This study tried not only to apply the novel variables in the field of educational technology, but also attempt to provide qualitative observations on the learning process based on a quantitative approach.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.4
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• pp.79-89
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• 2010

Recently, distributed video coding (DVC) has been actively studied for low complexity video encoder. The complexity of the encoder in DVC is much simpler than that of traditional video coding schemes such as H.264/AVC, but the complexity of the decoder in DVC increases. In this paper, we propose the Region-Of-Interest (ROI) based DVC with low decoding complexity. The proposed scheme uses the ROI, the region the motion of objects is quickly moving as the input of the Wyner-Ziv (WZ) encoder instead of the whole WZ frame. In this case, the complexity of encoder and decoder is reduced, and the bite rate decreases. Experimental results show that the proposed scheme obtain 0.95 dB as the maximum PSNR gain in Hall Monitor sequence and 1.87 dB in Salesman sequence. Moreover, the complexity of encoder and decoder in the proposed scheme is significantly reduced by 73.7% and 63.3% over the traditional DVC scheme, respectively. In addition, we employ the layered belief propagation (LBP) algorithm whose decoding convergence speed is 1.73 times faster than belief propagation algorithm as the Low-Density Parity-Check (LDPC) decoder for low decoding complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.