• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.506-507
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• 2012

In this paper, the mode control method for improving efficiency in photovoltaic AC module type interleaved flyback inverter. The proposed mode control method to increase the efficiency at the low power.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1477-1485
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• 2019

This paper proposes an effective model predictive current control (MPCC) that involves using 10 virtual voltage vectors to reduce the current harmonics and common-mode voltage (CMV) for a two-level five-phase voltage source inverter (VSI). In the proposed scheme, 10 virtual voltage vectors are included to reduce the CMV and low-order current harmonics. These virtual voltage vectors are employed as the input control set for the MPCC. Among the 10 virtual voltage vectors, two are applied throughout the whole sampling period to reduce current ripples. The two selected virtual voltage vectors are based on location information of the reference voltage vector, and their duration times are calculated using a simple algorithm. This significantly reduces the computational burden. Simulation and experimental results are provided to verify the effectiveness of the proposed scheme.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.1
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• pp.33-39
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• 2019

We propose a mechanical parameter estimation algorithm for surface-mounted permanent magnet synchronous motors (SPMSMs) using a sliding-mode observer (SMO) and an adaptive filter. The SMO estimates system disturbances in real time, which contain the information on mechanical parameters. A desirable feature that distinguishes the proposed estimation algorithm from other existing mechanical parameter estimators is that the adaptive filter estimates electromagnetic torque to improve the estimation performance. Moreover, the SMO acts as a low-pass filter to suppress the chattering effect, which enables the smooth output signals of the SMO. We verify the mechanical parameter estimation performance for SPMSM by conducting extensive experiments for the proposed algorithm.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.4
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• pp.14-19
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• 2010

In this paper, using interleaved power factor correction how to improve the inverter efficiency studied. Interleaved method can reduce the conduction losses and the inductor energy. Generally, critical conduction mode (CRM) boost PFC converter used low power level because of the high peak currents. if you use the interleaved mode, CRM PFC can be used medium or high power application. interleaved CRM PFC can reduce current ripple for higher system reliability and size of buck capacitor and EMI filter size. Interleaved CRM PFC that is installed in front of inverter can maintain the constant voltage regardless of the input voltage.

• Journal of Power Electronics
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• v.15 no.1
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• pp.246-255
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• 2015

This paper presents experimental results and its assessment of a variable-speed wind power generation system (VSWPGS) using permanent magnet synchronous generator (PMSG) and boost chopper circuit (BCC). Experimental results are obtained by a test bench with a wind turbine emulator (WTE). WTE reproduces the behaviors of a windmill by using servo motor drives. The mechanical torque references to drive the servo motor are calculated from the windmill wing profile, wind velocity, and windmill rotational speed. VSWPGS using PMSG and BCC has three speed control modes for the level of wind velocity to control the rotational speed of the wind turbine. The control mode for low wind velocity regulates an armature current of generator with BCC. The control mode for middle wind velocity regulates a DC link voltage with a vector-controlled inverter. The control mode for high wind velocity regulates a pitch angle of the wind turbine with a pitch angle control system. The hybrid of three control modes extends the variable-speed range. BCC simplifies the maintenance of VSWPGS while improving reliability. In addition, VSWPGS using PMSG and BCC saves cost compared with VSWPGS using a PWM converter.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1614-1622
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• 2014

A novel equivalent flux sliding-mode observer (SMO) is proposed for dual three-phase interior permanent magnet synchronous motor (DT-IPMSM) drive system in this paper. The DT-IPMSM has two sets of Y-connected stator three-phase windings spatially shifted by 30 electrical degrees. In this method, the sensorless drive system employs a flux SMO with soft phase-locked loop method for rotor speed and position estimation, not only are low-pass filter and phase compensation module eliminated, but also estimation accuracy is improved. Meanwhile, to get the regulator parameters of current control, the inner current loop is realized using a decoupling and diagonal internal model control algorithm. Experiment results of 2MW-level DT-IPMSM drives system show that the proposed method has good dynamic and static performances.

• The KIPS Transactions:PartC
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• v.19C no.2
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• pp.135-144
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• 2012

All the servers in a traditional server cluster environment are kept On. If the request load reaches to the maximum, we exploit its maximum possible performance, otherwise, we exploit only some portion of maximum possible performance so that the efficiency of server power consumption becomes low. We can improve the efficiency of power consumption by controlling power mode of servers according to load situation, that is, by making On only minimum number of servers needed to handle current load while making Off the remaining servers. In the existing power mode control method, they used a static policy to decide server power mode at a fixed time interval so that it cannot adapt well to the dynamically changing load situation. In order to improve the existing method, we propose a dynamic server power control algorithm. In the proposed method, we keep the history of server power consumption and, based on it, predict whether power consumption increases in the near future. Based on this prediction, we dynamically change the time interval to decide server power mode. We performed experiments with a cluster of 30 PCs. Experimental results show that our proposed method keeps the same performance while reducing 29% of power consumption compared to the existing method. In addition, our proposed method allows to increase the average CPU utilization by 66%.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.72-79
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• 2003

Classical designs of optical transimpedance preamplifier for p-i-n photodiode receiver circuits generally employ common source transimpedance input stages. In this paper, we explore the design of a class of current-mode optical transimpedance preamplifier based upon common gate input stages. A feature of current-mode optical transimpedance preamplifier is high gain and high bandwidth. The bandwidth of the transimpedance preamplifier can also be increased by the capacitive peaking technique. In this paper we included the development and application of a circuit analysis technique based on the minimum noise. We develop a general formulation of the technique, illustrate its use on a number of circuit examples, and apply it to the design and optimization of the low-noise transimpedance amplifier. Using the noise minimization method and the capacitive peaking technique we designed a transimpedance preamplifier with low noise, high-speed current-mode transimpedance preamplifier with a 1.57GHz bandwidth, and a 2.34K transimpedance gain, a 470nA input noise current. The proposed preamplifier consumes 16.84mW from a 3.3V power supply.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.248-254
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• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.