• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1077-1080
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• 1998

In this paper, a simple low-power current-mode CMOS wotage reference circuit is proposed. The reference circuit of enhancement-mode MOS transistors and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a threshold voltage. The designed circuit has been simulated using a $0.65\mu\textrm{m}$ n-well CMOS process parameters. The simulation results show that the reference circuit has a temperature coefficient less than $7.8ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.079%/V for a temperature range from $-30^{\circ}C$ to $130^{\circ}C$ and a VDD range from 4.0V to 12V. The power consumption is 105㎼ for VDD=5V and $T=30^{\circ}C.$ The proposed reference circuit can be designed to generate a wide range of reference voltages owing to its current-mode operation.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.1
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• pp.19-26
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• 2016

In this study, a bidirectional DC-DC converter for idle stop and go (ISG) is developed to reduce fuel consumption. A three-phase non-isolated half-bridge converter is selected through a design method by considering efficiency and volume. According to the state of charge of the batteries at both the low-voltage and high-voltage sides, buck mode, which charges a low-voltage battery from the generated motor energy, and boost mode, which provides power to the motor from the low- and high-voltage battery sides, are required in the ISG system. Hence, an autonomous and seamless bidirectional control method using a variable current limiter is proposed for mode change. A 1.8 kW engineering sample of the proposed converter has been built and tested to verify the validity of the proposed concept. The maximum efficiencies, including gate driver and control circuit losses, are 96.4% in charging mode and 96.1% in discharging mode.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.2
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• pp.133-138
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• 2014

This paper proposes a low power-loss averaging current mode control using a resistor and bypass switch. Generally, current sensing method using a resistor has a disadvantage of power loss which degrades the efficiency of the entire systems. On the other hand, proposed measurement technique operating with bypass-switch connected in parallel with sensing resistor can reduce power loss significantly the current sensor. An analog-circuited bypass driver is implemented and used along with an average-circuit mode controller. The bypass switch bypasses the sensing current with a small amount of power loss. In this paper, a 50[W] prototype average current mode boost converter has been implemented for the experimental verification.

• Journal of Electrical Engineering and Technology
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• v.6 no.1
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• pp.67-75
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• 2011

The development of electric vehicle power electronics system control, composed of DC-AC inverters and DC-DC converters, attract much research interest in the modern industry. A DC-AC inverter supplies the high-power motor torques of the propulsion system and utility loads of electric vehicles, whereas a DC-DC converter supplies the conventional low-power and low-voltage loads. However, the need for high-power bidirectional DC-DC converters in future electric vehicles has led to the development of many new topologies of DC-DC converters. The nonlinear control of power converters is an active research area in the field of power electronics. This paper focuses on the use of the fuzzy sliding mode strategy as a control strategy for buck-boost DC-DC converter power supplies in electric vehicles. The proposed fuzzy controller specifies changes in control signals based on the surface and knowledge on surface changes to satisfy the sliding mode stability and attraction conditions. The performance of the proposed fuzzy sliding controller is compared to that of the classical sliding mode controller. The satisfactory simulation results show the efficiency of the proposed control law, which reduces the chattering phenomenon. Moreover, the obtained results prove the robustness of the proposed control law against variations in load resistance and input voltage in the studied converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.3
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• pp.223-230
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• 2017

A low-cost BLDC motor with hall sensor is used to drive the position control of a facility security monitoring system in this paper. Low measurable frequency of the hall sensor signal in low-speed regions results in difficulty in obtaining accurate speed detection and position control. To improve system control performance, we propose a variable gain of position controller and stop mode control scheme according to the motor speed and error position with pre-set deceleration time. The proposed stop mode control scheme is activated around the stop position to forcibly move the BLDC motor to the stop position in low speed. In the proposed stop mode, the motor current is controlled by the actual speed with the reference rotating angle. The control performance of the proposed position control is verified through experiments at the actual rail guided facility security monitoring system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.8
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• pp.966-974
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• 2019

In this study, we propose a CMOS power amplifier (PA) using a bypass technique to enhance the efficiency in the low-power region. For the bypass structure, the common-gate (CG) transistor of the cascode structure of the driver stage is divided in two parallel branches. One of the CG transistors is designed to drive the power stage for high-power mode. The other CG transistor is designed to bypass the power stage for low-power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. The measured maximum output power is 20.35 dBm with a power added efficiency of 12.10%. At a measured output power of 11.52 dBm, the PAE is improved from 1.90% to 7.00% by bypassing the power stage. Based on the measurement results, we verified the functionality of the proposed bypass structure.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.4
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• pp.52-62
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• 1996

In this paper, a new continuous-time current-mode integrator as basic building block of the low-voltage analog current-mode active filters was proposed. Compared to the current-mode integrator which was proposed by Zele, the proposed current-mode integrator had higher unity gain frequency and output impedance in addition to lower power dissipation. And also, a current-mode third-order lowpass active filter was designed with the proposed current-mode integrator. The designed circuits were fabricated using the ORBIT's 1.2.mu.m double-poly double-metal CMOS n-well process. The experimental resutls of the active filter designed and fabricated for this research have shown that it has the performance of 44.5MHz cutoff frequency, 3.3mW power dissipation and the third-order active filter area was 0.12mm$^{2}$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.117-124
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• 2018

Wearable devices have become widespread. Fitness band is one of common wearable devices, providing useful functions. It helps users to monitor and collect their status such as heart rate and travel distance. Wearable devices, including fitness bands, are designed in small size and it ends up having small battery capacity. In that regard, it is necessary to expand the lifetime of wearable devices. Conventional power management scheme of wearable devices is based on DVFS Ondemand Governor and peripheral control by timeout event, such as turning off the LCD. In this paper, we propose a hybrid governor applying hardware supporting low power mode such as sleep mode to exploit the periodicity of fitness band task. In addition, we show hybrid governor outperforms in power consumption than conventional power management scheme of wearable devices based on Ondemand Governor through experiments.