• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.2
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• pp.1027-1035
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• 2014

The most important design factor for portable devices is power consumption. In this paper, in the early design stage of a mobile device which measures temperature and humidity a power consumption model will be proposed and then the overall power consumption will be estimated based on this model. We will verify previously the correctness of such estimated power consumption before implementation of the real device. That is our proposed design methodology based on power consumption model. An improved design method for efficiently reducing the current consumption in the idle mode is also presented. By implementing a real prototype of the mobile device for measuring temperature and humidity, the correctness of our proposed design methodology based on power consumption modeling will be verified.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.75-80
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• 2020

There are so many low power MAC protocols for wireless sensor network. IEEE802.15.4 among them has disadvantage of a large power consumption for synchronization. To save power consumption it use the superframe operation alternating sleep mode and awake mode. But latency is longer result from superframe operation. B-MAC can have shorter latency according to check interval. But transmitter consumes more power because of long preamble. And receiver is suffering from overhearing. In this paper, we use the adaptive check interval scheme[1] of B-MAC for enhancing the power consumption. Its maximum throughput and minimum delay is evaluated by comparing the proposed scheme with a typical single channel IEEE802.15.4.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.220-226
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• 2010

In this paper, an low power symbol detector is proposed for MIMO communication system with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing (SM) mode and spatial diversity (SD) mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block and using the dedicated clock MIMO modes, the power of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and synthesized to logic gates using a $0.13-{\mu}m$ CMOS standard cell library. The power consumption was estimated by using Synopsys Power CompilerTM, which is reduced by maximum 85%, compared with the conventional architecture.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2035-2044
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• 2016

In order to match the voltages between high voltage battery stacks and low voltage super-capacitors with a high conversion efficiency in hybrid energy sources electric vehicles (HESEVs), a high ratio bidirectional DC-DC converter with a synchronous rectification H-Bridge is proposed in this paper. The principles of high ratio step-down and step-up operations are analyzed. In terms of the bidirectional characteristic of the H-Bridge, the bidirectional synchronous rectification (SR) operation is presented without any extra hardware. Then the SR power switches can achieve zero voltage switching (ZVS) turn-on and turn-off during dead time, and the power conversion efficiency is improved compared to that of the diode rectification (DR) operation, as well as the utilization of power switches. Experimental results show that the proposed converter can operate bidirectionally in the wide ratio range of 3~10, when the low voltage continuously varies between 15V and 50V. The maximum efficiencies are 94.1% in the Buck mode, and 93.6% in the Boost mode. In addition, the corresponding largest efficiency variations between SR and DR operations are 4.8% and 3.4%. This converter is suitable for use as a power interface between the battery stacks and super-capacitors in HESEVs.

• Journal of Advanced Marine Engineering and Technology
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• v.30 no.4
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• pp.474-482
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• 2006

Generally almost all fatigue crack growth is affected by mode I. For this reason a study on mode I has concentrated in the field of fracture mechanics. However the fatigue crack initiation and growth in machines and structures usually occur in mixed mode loading. If there is any relationship between the cause of fracture in mixed mode loading and fracture surface, fracture surface pattern will be the main mean explaining reasons of fatigue fracture and obtaining further information about fracture process. In this paper low point shear-fatigue test with Aluminum alloy hi 5083-O is carried out from this prospect and then the mixed mode distribution of fracture surface is examined from the result after identifying the generation of fatigue crack surface pattern. It was found from the experimental results that the fatigue crack surface pattern and the fatigue crack shear direction are remarkably consistent. Furthermore It is possible that the analysis of distribution of mixed mode through the fatigue crack surface pattern.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.22-29
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• 1998

In this paper, an 10 bit current-mode CMOS A/D converter with a current predictor is designed with a CMOS process to be integrated into a portable image signal processing system. A current predictor let the number of comparator reduce to 70 percent compared with the two step flash architecture. The current magnitude of current reference is reduced to 68 percent with a modular current reference. The designed 10 bit Low-power current-mode CMOS A/D converter with a current predictor is simulated with HSPICE using 0.6$\mu\textrm{m}$ N-well single-poly triple-metal CMOS process parameters. It results in a conversion rate of 10MSamples/s. A power consumption is measured to be 94.4mW at single +5V supply voltage. The 10 bit A/D converter fabricated using the same process occupies the chip area of 1.8mm x 2.4mm.

• Journal of IKEEE
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• v.15 no.2
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• pp.134-142
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• 2011

This paper describes a tripple-mode high-efficiency DC-DC buck converter. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(100mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~100mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 96.4% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is 1.15mm ${\times}$ 1.10mm including pads.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.411-414
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• 2011

This paper describes a tripple-mode DC-DC buck converter with DPSS Fucntion. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(80mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~80mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 97.02% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is $1465um{\times}895um$ including pads.

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.1-7
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• 2010

This paper presents a low power digital PLL architecture and design for implementation of the PLL-based frequency synthesizers. In the proposed architecture, a wide band digital logic quadricorrelator is used for preliminary frequency detector and a narrow band digital logic quadricorrelator is used for final DCO control. Also, a circuit technique for reducing leakage current is adopted in order to minimize the standby mode power consumption of the deactivated block. The proposed digital PLL is designed and verified by MyCAD with MOSIS 1.8V $0.35{\mu}m$ CMOS technology, and the simulation results show that the power consumption can be lowered by more than 20%.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.8
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• pp.1101-1107
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• 2013

A light emitting diodes(LED) lighting has been increasingly used due to its low power consumption, long life time, high efficiency, and environment friendly characteristics. Also various power converters has been applied to drive these LED lighting. Among many power converters, a LLC resonant converter could be applied for LED lighting because of its high efficiency and high power density. Furthermore, the function of power factor correction(PFC) might be added. In this paper, 1-stage asymmetrical LLC resonant converter is proposed. The proposed converter performs both input-current harmonics reduction and PFC using the discontinuous conduction mode(DCM). The proposed 1-stage LLC resonant converter approach has the lower voltage stress across switching devices and achieve the zero voltage switching(ZVS) in switching devices. To verify the performance of the proposed converter, simulation and experimental results from a 300[W] prototype are provided.