• Journal of Power Electronics
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• v.10 no.3
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• pp.219-227
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• 2010

Telecom supplies need to conform to low Total Harmonic Distortion (THD) and high Power Factor (PF) as per IEC 61000-3-2 and IEEE 519-1992 standards. These high rating power supplies use a three phase utility in which low THD and high PF are realized via various passive and active wave shaping schemes. In this paper, a new design for three phase telecom power supplies is presented with circuit parameter values optimized for high performance in terms of a low THD, high PF, low ripple and high line and load regulation using a suitable combination of various strategies. The performance of the power supply is validated by extensive simulations.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.110-120
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• 2016

A power-efficient neuromodulator is needed for implantable systems. In spite of their stimulation signal's simplicity of wave shape and waiting time of MCU(micro controller unit) much longer than execution time, there is no consideration for low-power design. In this paper, we propose a novel of low-power algorithm based on the characteristics of stimulation signals. Then, we designed and implement a neuromodulation software that we call NMS(neuro modulation simulation). In order to implement low-power algorithm, first, we analyze running time of every function in existing NMS. Then, we calculate execution time and waiting time for these functions. Subsequently, we estimate the transition time between active mode (AM) and low-power mode (LPM). By using these results, we redesign the architecture of NMS in the proposed low-power algorithm: a stimulation signal divided into a number of segments by using characteristics of the signal from which AM or LPM segments are defined for determining the MCU power reduces to turn off or not. Our experimental results indicate that NMS with low-power algorithm reducing current consumption of MCU by 76.31 percent compared to NMS without low-power algorithm.

• Journal of Sensor Science and Technology
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• v.32 no.6
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• pp.432-440
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• 2023

This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 V_PP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm². Experimental evaluations showed a 0.59 µV_RMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.388-392
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• 2012

In this paper, a sampler model for the P-type current mode control employing low pass filter is proposed. Even though the frequency response of the compensator used in a P-type current mode control employing low pass filter is similar to that of P-type compensator, the sampler model has to be obtained from the method used in PI-type current mode control. In order to show the usefulness of the proposed method, prediction results of the proposed model are compared to those from the circuit level simulator, PSIM.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.57-64
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• 2007

This paper proposed the low power texture cache for mobile 3D graphics accelerators. It is very important to reduce the leakage power in the standby mode for mobile 3D graphics accelerators and the memory access latency of texture mapping in the active mode which needs a large memory bandwidth. The proposed structure reduces the leakage power using variable threshold values of power mode transitions according to the selected texture filtering algorithms of application programs, which has the run time gain for texture mapping. In the trace driven cache simulation the proposed structure shows the best 7% performance gain to the previous MSA cache according to the new performance metric considering both normalized leakage power and run time impact.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.431-437
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• 2012

PV simulators are essential equipment for testing power conditioning systems (PCS) which are one of an important part in PV generator systems, for testing before shipment. High dynamic PV simulator is required since MPPT(Maximum Power Point Tracking) test procedure has been established by EN50530 regulation recently. Most high quality PV simulator prevailed in the market is linear type which however has low efficiency. This paper proposes design guide lines for the power stage and LCL type filter cooperating with a switching mode PV simulator that shows high efficiency and very low power consumption. Proposed theory is verified by experiment.

• ETRI Journal
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• v.31 no.2
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• pp.243-245
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• 2009

A novel ultra-low-power readout circuit for a pH-sensitive ion-sensitive field-effect transistor (ISFET) is proposed. It uses an ISFET/reference FET (REFET) differential pair operating in weak-inversion and a simple current-mode metal-oxide semiconductor FET (MOSFET) translinear circuit. Simulation results verify that the circuit operates with excellent common-mode rejection ability and good linearity for a single pH range from 4 to 10, while only 4 nA is drawn from a single 1 V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.6
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• pp.719-725
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• 2019

We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.210-212
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• 2018

A new switching mode has been proposed to obtain high power factor and low THD in single stage AC-DC converter. The conventional voltage mode control in critical conduction mode distorts input current shape with poor THD in flyback topology. Once TRIAC dimmer is connected, visible flicker in the LED lamp is easily detected due to a lack of TRAIC holding current near the input voltage zero cross. The newly proposed method can shape the input current by providing a desired reference voltage so that low THD is obtained by ideal sinusoidal input current in case of no dimmer connection and flat input current performs good TRIAC dimmer compatibility in phase-cut dimming condition. To confirm the validity of the proposed method, theoretical analysis and experimental result from 8W dimmable LED lighting system are presented.

• The KIPS Transactions:PartA
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• v.15A no.2
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• pp.69-74
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• 2008

This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The $16\;{\times}\;16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung $0.35\;{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.