• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.10
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• pp.713-719
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• 2013

Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have optimal designed planar and trench gate power MOSFET for high breakdown voltage and low on resistance. When we have designed $6,580{\mu}m{\times}5,680{\mu}m$ of chip size and 20 A current, on resistance of trench gate power MOSFET was low than planar gate power MOSFET. The on state voltage of trench gate power MOSFET was improved from 4.35 V to 3.7 V. At the same time, we have designed unified field limit ring for trench gate power MOFET. It is Junction Termination Edge type. As a result, we have obtained chip shrink effect and low on resistance because conventional field limit ring was convert to unify.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.91-94
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• 2000

This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65$\mu\textrm{m}$, 3.3V supply.

• 한국연소학회:학술대회논문집
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• 2013.06a
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• pp.129-132
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• 2013

The low rank coal combustion and biomass-coal co-firing characteristics were reviewed on this study for the power plant construction. The importance of using low rank coal(LRC) for power plant is increasing gradually due to power generation economy and biomass co-firing is also concentrated as power source because it has carbon neutral characteristics to reduce green-house effect. The combustion characteristics of low rank coal and biomass for a 310MW coal firing power plant and a 100MW biomass and coal co-firing power plant were studied to apply into actual power plant design and optimized the furnace and burner design.

• Journal of Korea Society of Digital Industry and Information Management
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• v.4 no.3
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• pp.77-83
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• 2008

In this paper, CPLD low power technology mapping for reuse module design under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.

• Journal of Satellite, Information and Communications
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• v.8 no.3
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• pp.10-14
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• 2013

In this paper, when applying current-mode circuit design technique showing constant power dissipation none the less operation frequency, to the low power design of dynamic voltage frequency scaling, we introduce the low power current-mode circuit design technique applying MOSFET in sub-threshold region, in order to solve the problem that has large power dissipation especially on the condition of low operating frequency. BSIM 3, was used as a MOSFET model in circuit simulation. From the simulation result, the power dissipation of the current memory circuit with sub-threshold MOSFET showed $18.98{\mu}W$, which means the consumption reduction effect of 98%, compared with $900{\mu}W$ in that with strong inversion. It is confirmed that the proposed circuit design technique will be available in DVFS using a current-mode circuit design.

• Journal of Magnetics
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• v.19 no.3
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• pp.273-281
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• 2014

This paper presents an innovative design for a low-speed, direct-drive, axial-flux permanent-magnet (AFPM) generator with a coreless stator and rotor that is intended for application to small wind turbine power generation systems. The performance of the generator is evaluated and optimized by means of comprehensive 3D electromagnetic finite element analysis. The main focus of this study is to improve the power output and efficiency of wind power generation by investigating the electromagnetic and structural features of a coreless AFPM generator. The design is validated by comparing the performance achieved with a prototype. The results of our comparison demonstrate that the proposed generator has a number of advantages such as a simpler structure, higher efficiency over a wide range of operating speeds, higher energy yield, lighter weight and better power utilization than conventional machines. It would be possible to manufacture low-cost, axial-flux permanent-magnet generators by further developing the proposed design.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.12-19
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• 1997

In this paper, we present a logic synthesis algorithm for low powr design fo combinational circuits. The proposed algorithm reduces power dissipation by eliminating unnecessary signal transitions. The proposed algorithm restructures a given circuit by using a kernel as prediction logic in a precomputation-based scheme such that switching activity of circuit can be minimized. Experimental results show that the system is efficient for low power design of combinational circuits.

• Journal of Power Electronics
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• v.7 no.4
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• pp.318-327
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• 2007

The design and performance analysis of a power factor corrected (PFC), single-phase, single switch flyback buck-boost ac-dc converter is carried out for low power battery charging applications. The proposed configuration of the flyback buck-boost ac-dc converter consists of only one switch and operates in discontinuous current mode (DCM), resulting in simplicity in design and manufacturing and reduction in input current total harmonic distortion (THD). The design procedure of the flyback buck-boost ac-dc converter is presented for the battery charging application. To verify and investigate the design and performance, a simulation study of the flyback buck-boost converter in DCM is performed using the PSIM6.0 platform. A laboratory prototype of the proposed single switch flyback buck-boost ac-dc converter is developed and test results are presented to validate the design and developed model of the system.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.625-626
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• 2006

An Ultra low power super-regenerative oscillator was implemented with on-chip inductor and quench signal generator. The super-regenerative oscillator detects the signal level as low as -70dBm while consuming only 0.48mA at 1.5V supply voltage. These results indicate that the super-regenerative oscillator can be outstanding candidate the simple, ultra low power receiver design.

• Journal of IKEEE
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• v.12 no.4
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• pp.239-245
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• 2008

In this paper, a dc-dc power converter scheme with the FPGA based technology is proposed to apply for solar power system which has many features such as the good waveform, high efficiency, low switching losses, and low acoustic noises. The circuit configuration is designed by the conventional control type converter circuit using the isolated dc power supply. This new scheme can be more widely used for industrial power conversion system and many other purposes. Also, I proposed an efficient photovoltaic power interface circuit incorporated with a FPGA based DC-DC converter and a sine-pwm control method full-bridge inverter. The FPGA based DC-DC converter operates at high switching frequency to make the output current a sine wave, whereas the full-bridge inverter operates at low switching frequency which is determined by the ac frequency. As a result, we can get a 1.72% low THD in present state using linear control method. Moreover, we can use stepping control method, we can obtain the switching losses by Sp measured as 0.53W. This paper presents the design of a single-phase photovoltaic inverter model and the simulation of its performance.