• 전기학회논문지P
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• 제60권3호
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• pp.133-137
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• 2011

The purpose of smart grid is the low $CO_2$ through expansion of renewable energy. To achieve the purpose of smart grid, typical radial power distribution system will be changed to loop power distribution system. The loop power distribution system have many advantages such as low power loss, low voltage drop, and increase of connection of renewable energy. In this paper, the algorithm for minimization of interrupted section of power distribution system is proposed through communication between circuit breaker and recloser in loop power distribution system. The proposed algorithm is proved through case studies about reliability evaluation

• 전자공학회논문지C
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• 제34C권12호
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• pp.20-27
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• 1997

In this paper, a multiplying digital-to-analog converter (MDAC) circuit for low-power high-resolution CMOS algorithmic A/D converters (ADC's) is proposed. The proposed MDAC is designed to operte properly at a supply at a supply voltge between 3 V and 5 V and employs an analog0domain power reduction technique based on a bias switching circuit so that the total power consumption can be optimized. As metal-to-metal capacitors are implemented as frequency compensation capacitors, opamps' performance can be varied by imperfect process control. The MDAC minimizes the effects by the circuit performance variations with on-chip tuning circuits. The proposed low-power MDAC is implementd as a sub-block of a 10-bit 200kHz algorithmic ADC using a 0.6 um single-poly double-metal n-well CMOS technology. With the power-reduction technique enabled, the power consumption of the experimental ADC is reduced from 11mW to 7mW at a 3.3V supply voltage and the power reduction ratio of 36% is achieved.

• Journal of information and communication convergence engineering
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• 제7권1호
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• pp.52-56
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• 2009

In this research, we have studied the development of dc-dc converter suitable for the driving of mobile instruments by using a dye-sensitized solar cell(DSC). We also have designed a interlocking circuit. The circuit makes power generation be saved in one battery and concurrently be discharged in the other battery. As this application, mobile devices such as MP3, cellular phone are operated by using power generator from DSC during the daytime and they can be operated by using the saving energy of the daytime during the night. Consequently, it has a simple and robust circuit configuration. Besides, we designed dc-dc converter circuit to drive low power instruments by using NMOS switch and PMOS rectifier. Operational modes are analysed, and then validity of the proposed interface circuit is verified through DCS.

• 대한전기학회논문지:전력기술부문A
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• 제54권9호
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• pp.434-440
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• 2005

This paper describes an optimized Scheme of reactive-power compensation for the low short-circuit-ratio AC system interconnected with the HVDC system. An HVDC system interconnected with tile low SCR AC system is vulnerable to the ac voltage variation, which brings about the commutation failure of the converter. This problem can be solved using optimized compensation of reactive power. In this study, a benchmark system for HVDC system interconnected with low SCR AC system is derived using PSS/E simulation. Then an optimized srheme for reactive power compensation was derived using integer programming. The feasibility of proposed scheme was analyzed through silnulations with PSS/E and PSCAD/EMTDC. The proposed scheme can compensate the reactive power accurately and minimize the number of switching for harmonic filters and shunt reactors.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.723-727
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• 2004

A new high-performance and low cost single switch energy recovery display driver for an AC plasma display panel (PDP) is proposed. Since it is composed of only one auxiliary power switch, two small inductors, and eight diodes compared with the conventional circuit consisting of four auxiliary power switches, two small inductors, eight power diodes, and two external capacitors, it features a much simpler structure and lower cost. Nevertheless, since the rootmean-square (RMS) value of the inductor current is very small, it also has very desirable advantages such as n low conduction loss and high efficiency. Furthermore, there are no serious voltage-drops caused by the large gas-discharge current with the aid of the discharge current compensation, which can also greatly reduce the current flowing through power switches and maintain the panel to light at n lower sustaining voltage. In addition, all main power switches are turned on under the zero-voltage switching (ZVS) and thus, the proposed circuit has a improved EMI, increased reliability, and high efficiency. Therefore, the proposed circuit will be well suited to the wall hanging PDP TV. To confirm the validity of the proposed circuit, circuit operations, features,and design considerations are presented and verified experimentally on a 6-inch PDP, 50kHz-switching frequency, and sustaining voltage 141V based prototype.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.221-224
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• 2004

This paper proposed an ultra low-power CMOS exponential voltage-mode circuit using the Pseudo-exponential function for realizing the exponential characteristics. The proposed circuit provides high dB-linear output voltage range at low-voltage applications. In a $0.25\;\mu m$ CMOS process, the simulations show more than 35 dB output voltage range and 26 dB with the linearity error less than $\pm0.5\;dB.$ The average current consumption is less than 80 uA. The proposed circuit can be used for the design of an extremely low-power variable gain amplifier (VGA) and automatic gain control (AGC).

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.625-626
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• 2006

An Ultra low power super-regenerative oscillator was implemented with on-chip inductor and quench signal generator. The super-regenerative oscillator detects the signal level as low as -70dBm while consuming only 0.48mA at 1.5V supply voltage. These results indicate that the super-regenerative oscillator can be outstanding candidate the simple, ultra low power receiver design.

• Transactions on Electrical and Electronic Materials
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• 제14권5호
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• pp.235-241
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• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 F
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• pp.2204-2206
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• 1997

A novel zero voltage and zero current switching (ZVZCS) full bridge (FB) PWM converter with a low output current ripple is proposed. The proposed circuit improve the demerits of the previously presented ZVBCS-FB-PWM converters[5-8] such as use of lossy components or additional active switches. A simple auxiliary circuit which includes neither lossy components nor active switches provides ZVZCS conditions to primary switches, ZVS for leading-leg switches and ZCS for lagging-leg switches. In addition, this proposed circuit reduces a output current ripple considerably. Many advantages including simple circuit topology, high efficiency, low cost and low current ripple make the new converter attractive far high power (> 1kW) applications.

• 정보처리학회논문지A
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• 제15A권5호
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• pp.243-248
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• 2008

본 논문은 다중 문턱전압 CMOS를 이용하여 저 전력 특성을 갖는 캐리 예측 가산기 (carry look-ahead adder)를 설계하였으며, 이를 일반적인 CMOS 가산기와 특성을 비교하였다. 전파 지연시간이 긴 임계경로에 낮은 문턱전압 트랜지스터를 사용하여 전파 지연시간을 감소시켰다. 전파 지연시간이 짧은 최단경로에는 높은 문턱전압 트랜지스터를 사용하여 회로전체의 소비전력을 감소시켰으며, 그 외의 논리블럭들은 정상 문턱전압의 트랜지스터를 사용하였다. 설계한 가산기는 일반적인 CMOS 회로와 비교하여 소비전력에서 14.71% 감소하였으며, 소비전력과 지연 시간의 곱에서 16.11%의 성능향상이 있었다. 이 회로는 삼성 $0.35{\mu}m$ CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.