• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.583-591
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• 2008

OFDM (orthogonal frequency division multiplexing) has serious problem of high PAPR (peak-to-average power ratio). Recently, CI/OFDM (carrier interferometry OFDM) system has been proposed for the low PAPR. However, CI/OFDM system shows another problem of ICI because of phase offset mismatch due to the phase noise. In this paper, to simultaneously reduce the PAPR and ICI effects, we propose an A-CI/OFDM (advanced-CT/OFDM). This method improves the BER performance by use of the margin of phase offset at CI codes. Propose system to reduce the effect the phase noise, even though it shows a little bit higher PAPR than conventional CI/OFDM, so we apply the PTS among the PAPR reduction techniques to proposed system to mitigate this problem. Therefore, it improves the total BER performance because the proposed method can decrease the effect of phase noise and get the gain in PAPR reduction performance. From the simulation results, we can show the performance comparison between the conventional OFDM, CI/OFDM and A-CI/OFDM.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.1
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• pp.84-90
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• 2010

In this paper, a novel voltage-controlled oscillator (VCO) using the harmonic control circuit based on the composite right/left-handed (CRLH) transmission lines (TLs) is presented to reduce the phase noise without the reduction of the frequency tuning range and miniaturize the circuit size. The phase noise is reduced by the novel harmonic control circuit having the short impedances for the second- and third-harmonic components. The proposed harmonic control circuit is designed by using the CRLH TLs with the dual-band characteristic by the frequency offset and phase slope of the CRLH TLs. The high-Q resonator has been used to reduce the phase noise, but has the problem of the frequency tuning range reduction. However, the frequency tuning range of the proposed VCO has not been reduced because the phase noise has been reduced without the high-Q resonator. The miniaturization of the circuit size is achieved by using the CRLH TLs instead of the conventional right-handed (RH) TLs. The phase noise of VCO is -119.17 ~ -117.50 dBc/Hz at 100 kHz in the tuning range of 5.731 ~ 5.938 GHz.

• Current Optics and Photonics
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• v.2 no.2
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• pp.165-171
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• 2018

Fourier ptychographic microscopy (FPM) is a recently proposed computational imaging method that achieves both high resolution (HR) and wide field of view. In the FPM framework, a series of low-resolution (LR) images at different illumination angles is used for high-resolution image reconstruction. On the basis of previous research, image noise can significantly degrade the FPM reconstruction result. Since the captured LR images contain a lot of dark-field images with low signal-to-noise ratio, it is very important to apply a noise-reduction process to the FPM raw dataset. However, the thresholding method commonly used for the FPM data preprocessing cannot separate signals from background noise effectively. In this work, we propose an improved thresholding method that provides a reliable background-noise threshold for noise reduction. Experimental results show that the proposed method is more efficient and robust than the conventional thresholding method.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.4
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• pp.43-47
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• 2024

This paper introduces a phased-array single-channel transceiver beamformer IC built using 65nm CMOS technology, covering the 8-16 GHz range and targeting the X and Ku bands for radar and satellite communications. Each signal path in the IC features a low noise amplifier (LNA), power amplifier (PA), phase shifter (PS), and variable gain amplifier (VGA), which allow for phase and gain adjustments essential for beam steering and tapering control in typical beamforming systems. Test results show that the phase-compensated VGA offers a gain range of 15 dB with 0.25 dB increments and an RMS gain error of 0.27 dB. The active vector modulator phase shifter delivers a 360° phase range with 2.8125° steps and an RMS phase error of 3.5°.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.6
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• pp.691-699
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• 2012

In this paper, we present a Vt-DRO with a low phase noise, which is achieved by improving the coupling structure between the dielectric resonator and microstrip line. The Vt-DRO is a closed-loop type and is composed of 3 blocks; dielectric resonator, phase shifter, and amplifier. We propose a mathematical estimation method of phase noise, using the group delay of the resonator. By modifying the coupling structure between the dielectric resonator and microstrip line, we achieved a group delay of 53 nsec. For convenience of measurement, wafer probes were inserted at each stage to measure the S-parameters of each block. The measured S-parameter of the Vt-DRO satisfies the open-loop oscillation condition. The Vt-DRO was implemented by connecting the input and output of the designed open-loop to form a closed-loop. As a result, the phase noise of the Vt-DRO was measured as -132.7 dBc/Hz(@ 100 kHz offset frequency), which approximates the predicted result at the center frequency of 5.3 GHz. The tuning-range of the Vt-DRO is about 5 MHz for tuning voltage of 0~10 V and the power is 4.5 dBm. PFTN-FOM is -31 dBm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.1
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• pp.1-8
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• 2015

In this paper, a double-input single-output architecture of a LNA(Low Noise Amplifier) is presented to enable to be devised for light weight and small-sized OTM(On-The-Move) satellite communication system suitable to be mounted on vehicles. In spite of advantages of the double-input single-output architecture of a LNA such as reduction of the number of physical channels, it results in time-varying phase error between a fundamental mode path and a high-order mode path. This paper shows that the error can be corrected by adding pilot signals to the LNA and using signal processing, and also gives the measurement data to use the method mentioned above.

• Structural Engineering and Mechanics
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• v.75 no.4
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• pp.435-444
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• 2020

Ultrasonic guided wave testing is a very promising non-destructive testing method for rails, which is of great significance for ensuring the safe operation of railways. On the basis of the semi-analytical finite element (SAFE) method, a analytical model of 59R2 grooved rail was proposed, which is commonly used in the ballastless track of modern tram. The dispersion curves of ultrasonic guided waves in free rail and supported rail were obtained. Sensitivity analysis was then undertaken to evaluate the effect of rail elastic modulus on the phase velocity and group velocity dispersion curves of ultrasonic guided waves. The optimal guided wave mode, optimal excitation point and excitation direction suitable for detecting rail integrity were identified by analyzing the frequency, number of modes, and mode shapes. A sinusoidal signal modulated by a Hanning window with a center frequency of 25 kHz was used as the excitation source, and the propagation characteristics of high-frequency ultrasonic guided waves in the rail were obtained. The results show that the rail pad has a relatively little influence on the dispersion curves of ultrasonic guided waves in the high frequency band, and has a relatively large influence on the dispersion curves of ultrasonic guided waves in the low frequency band below 4 kHz. The rail elastic modulus has significant influence on the phase velocity in the high frequency band, while the group velocity is greatly affected by the rail elastic modulus in the low frequency band.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.12
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• pp.649-654
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• 2003

The simplest method for measuring output currents of the three phase inverters is to measure them with three current sensors such as hall sensors. This method requires at least two current sensors, and these types of sensors are somewhat expensive. More economical method is measuring DC link current with a simple shunt resistor, then, reconstructing output current using the DC link current value and the switching status. However, in low speed region, the measurement becomes difficult and even impossible due to the requirement of minimum switching duration for A/D conversion. These problems can be overcome by limitation of switching duration. Limitation of switching, however, causes voltage and current distortion. Owing to compensation, distortion can be effectively suppressed. However these increase acoustic noise due to increment of current ripple. In this paper, a current measurement method is proposed, which can reduce minimum switching duration resulting in reduction of acoustic noise. The validity of proposed method is confirmed through experiment.

• Journal of the Korean Institute of Navigation
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• v.6 no.1
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• pp.1-18
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• 1982

In this paper, author studied on the elementary data required for the design of the receiver of Pseudo Noise (PN) phase modulation communication adopted in Global Positioning System(GPS). By computer simulation technique, the phase modulator, filters, and PN generator are designed, and also required bandwidth of R-F amplifier for carrier frequency in phase modulation system is investigated. It is verified that the optimum bandwidth is about 3 times of the PN frequency and almost independent of the carrier frequency. And the low pass filter required for demodulation of slow Boolean data is also found to be about 60 times of the data signal frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.