• Advances in pediatric surgery
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• v.1 no.1
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• pp.27-32
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• 1995

Jejunal and ileal atresias are the most common cause of congenital intestinal obstruction and accounts for about 1/3 of all cases of intestinal obstruction in newborns. Despite the relative frequency of this anomaly, its survival rate was less than 10% up to 1950, more recently the survival rate has risen rapidly to 90% with the introduction of modern surgical techniques and the use of total parenteral nutrition. In 1969 Thomas described a tapering jejunoplasty to manage the discrepancy in the size of the proximal dilated lumen & contracted distal lumen, and to preserve absorptive surface when the dilated jejunum involved a long length, and Grosfeld et al.(1979) facilitated this method by using GIA staplers. Author have also used GIA stapler to resect the antimesenteric portion of the dilated proximal bowel in 8 cases of jejunoileal atresias with good results. The following results were obtained ; 1. There we 3 jejunal atresias & 5 ileal atresias, and male to female sex ratio was 5 : 3. 2. The type of atresia was as follows ; type IIIa was 3 cases, type IIIb was 4 cases, type IIIb+IV was 1 case. 3. In non-complication cases(5 cases), the mean hospital day was 16 days, and oral feeding was feasible from 6.2 days after operation. 4. The complications(anastomotic leakage, pneumonia) were frequently occurred in type IIIb cases and in low birth weight cases(75%). 5. Mortality rate was 25% including DAMA(discharge against medical advice) discharge case.

• Journal of the Korean GEO-environmental Society
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• v.18 no.1
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• pp.49-58
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• 2017

Due to low annual average temperature, road tunnel lining in domestic cold region (Gangwon province) experiences durability problems. The financial and human damage due to cracks, breakout, exfoliation and water leakage increases every year. However, domestic research on effect of temperature on road tunnel lining damage is insufficient. Thus, this research has investigated 70 tunnels located in cold region (Gangwon-do) to analyze damage status. Furthermore, by contrasting damage on tunnels in relatively warm Gangneung area with those in relatively cold Hongcheon area, the effect of temperature on road tunnel lining damage was analyzed.

• Transactions of the Korean hydrogen and new energy society
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• v.29 no.4
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• pp.370-377
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• 2018

Ball valve has been widely used in the field of high-pressure gas pipeline as an important component because of its low flow resistance and good leakage performance. The present paper focuses on the flow nature at the downstream of the ball valve used for gas pipelines according to valve opening rates. Steady 3-D RANS equations, SC/Tetra, have been introduced to analyze the flow characteristics inside the ball valve. Numerical boundary conditions at the inlet and outlet of the valve system are imposed by mass flow-rate and pressure, respectively. Velocity distributions obtained by numerical simulation are compared with respect to the valve opening rates of 30, 50, and 70%. Cavity distributions, asymmetry flow velocity and the flow stabilization point at each opening rate are also compared. When the valve opening rates are 30 and 50%, the flow stabilization requires the sufficient length of 10D or more due to the influence of the recirculation flow at the downstream of the valve.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.12
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• pp.755-760
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• 1999

Various fluoride films were investigated for a gate insulator of thin film transistor application. Conventional oxide containing materials like $SiO_2\;Ta_2O_5\; and \; Al_2O_3$ exhibited high interface states which lead to an increased threshold voltage and poor stability of TFT. In this paper, we investigated gate insulators using a binary matrix system of fluoride such as $CaF_2,\; SrF_2\; MgF_2,\; and\; BaF_2$. These materials exhibited an improvement in lattice mismatch, interface state and electrical stability. MIM and MIS devices were employed for an electrical characterization and structural property examination. Among the various fluoride materials, $CaF_2$ film showed an excellent lattice mismatch of 5%, breakdown electric field higher than 1.2MV/cm and leakage current density of $10^{-7}A/cm^2$. MIS diode having $Ca_2$ film as an insulation layer exhibited the interface states as low as $1.58\times10^{11}cm^{-2}eV^{-1}$. This paper probes a possibility of new gate insulator materials for TFT applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.172-176
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• 2002

This paper describes a MEMS-based micro-fluxgate magnetic sensing element using Ni$\_$0.8/Fe$\_$0.2/ film formed by electroplating. The micro-fluxgate magnetic sensor composed of a thin film magnetic core and micro-structured solenoids for the pick-up and the excitation coils, is developed by using MEMS technologies in order to take advantage of low-cost, small size and lower power consumption in the fabrication. A copper with 20um width and 3um thickness is electroplated on Cr(300${\AA}$)/Au(1500${\AA}$) films for the pick-up(42turn) and the excitation(24turn) coils. In order to improve the sensitivity of the sensing element, we designed the magnetic core into a rectangular-ring shape to reduce the magnetic flux leakage. An electroplated permalloy film with the thickness of 3 $\mu\textrm{m}$ is obtained under 2000Gauss to induce magnetic anisotropy. The magnetic core has the high DC effective permeability of ∼1,100 and coercive field of -0.1Oe. The fabricated sensing element using rectangular-ring shaped magnetic film has the sensitivity of about 150V/T at the excitation frequency of 2MHz and the excitation voltage of 4.4Vp-p. The power consumption is estimated to be 50mW.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1631-1633
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• 2001

In manufacturing processes, various and suitable pulse shapes are required for the purpose of material processing and the pulseshape is regarded as a dominant factor due to the specific property of processing materials. Therefore, in this study, a variable pulse width, high duty cycle Pulse Forming Network(PFN) is constructed by time sequently. The power supply for this experiment consists of three switching circuits. The PFN elements operate at low voltage and drive the primary of HV leakage transformer. The secondary of the transformer has a full-wave rectifier, which passes the pulse energy to the load in a continuous sequence of properly phased and nested increments. We investigated laser pulse width as various delay time among three switching circuit. As a result, we tan obtain various laser pulse width from about 4ms to 10ms. The maximum laser pulse width obtained at this experiment was about 10ms at delay time of 4ms among each switching circuit.

• The Korean Journal of Ceramics
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• v.6 no.1
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• pp.74-77
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• 2000

Ta-doped PZT thin films prepared by reactive co-sputtering method could be transformed into single grained perovskite structure utilizing physical etching of Pt bottom electrode. It is found that PZT perovskite phase on damaged (111) Pt electrode by IMD was more easily crystallized than random oriented Pt electrode and less crystallized than (111) Pt electrode. This shows that amorphized Pt electrode surface by IMD process has an effect on crystallization of PZT perovskite phase. 40$\mu\textrm{m}\times40\mu\textrm{m}$ square shape single grain PZT array could be obtained utilizing the difference of incubation time for nucleation of rosettes between ion damaged Pt and (111) oriented Pt electrode. Single grained PZT thin films show low leakage current density of $1\times10^{-7}$ A/$\textrm{cm}^2$ and high break down field of 440kV/cm. The loss of remanent polarization after $10^{11}$ cycles was less than 15% of initial value.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.912-915
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• 2004

Inductors material utilized in the downsizing passive devices and Rf components requires the physical and electrical properties at given area such as inductors thickness reduction, inductance and q-factor increase, low leakage current and thermal stability. In this study, Spiral inductors on the $SiO_2/Si$(100) substrate were fabricated by the magnetron sputtering method. Cu thin film with the thickness of $2{\mu}m$ was deposited on the substrate. Also we fabricated square inductors through the wet chemical etching technique. The inductors are completely specified by the turn width and the spacing between spirals. Both the width and spacing between spirals were varied from 10 to $60{\mu}m$ and from 20 to $70{\mu}m$, respectively. Inductance and Q factor dependent on the RF frequency were investigated to analyze performance of inductor arrays

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12
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• pp.1071-1076
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• 2003

The nonlinear properties and their stability of ZPCCD- based varistors, which are composed of ZnO P $r_{6}$ $O_{ll}$ - CoO-C $r_2$ $O_3$-D $y_2$ $O_3$-based ceramics, were investigated in the D $y_2$ $O_3$ content range of 0.0∼2.0 mol%. The incorporation of D $y_2$ $O_3$ greatly affected the nonlinear properties and the best nonlinearity was obtained from 0.5 mol% D $y_2$ $O_3$ with nonlinear exponent of 66.6 and leakage current of 1.2 $\mu$A. Further addition of D $y_2$ $O_3$ deteriorated the nonlinear properties. In stability against DC accelerated aging stress state: 0.95 $V_{1mA}$/15$0^{\circ}C$/24 h, the 0.5 mol％ D $y_2$ $O_3$-doped varistor exhibited the highest stability, in which the variation rate of varistor voltage and nonlinear exponent are -1.9% and 10.5%, respectively. The remainder varistors resulted in thermal runaway due to low density of ceramics.s.s.

• Transactions on Electrical and Electronic Materials
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• v.11 no.3
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• pp.93-105
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• 2010

Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.