• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.79-82
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• 2003

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to $V_{ref}-V_{TH}$, where $V_{ref}=V_{DD}-nV_{TH}$. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we propose a low-power $4\times4$ bit parallel multiplier. The proposed circuits are simulated with HSPICE under $0.35{\mu}m$ CMOS standard technology. Compare to the previous works, this circuit can reduce the power consumption rate of 11.2% and the power-delay product of 10.3%.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.96-96
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• 2007

Low voltage organic TFTs (OTFTs) and ZnO based TFTs (<5V), utilizing room temperature deposited $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN) thin films were recently reported, pointing to high-k gate insulators as a promising route for realizing low voltage operating flexible electronics. $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN) thin film is one of the most promising materials for gate insulator because of its large dielectric constant (~60) at room temperature. However their tendency to suffer from relatively high leakage current at low electric field (>0.3MV/cm) hinder the application of BZN thin films for gate insulator. In order to improve leakage current characteristics of BZN thin film, we mixed 30mol% MgO with 70mol% BZN and their dielectric and electric properties were characterized. We fabricated field-effect transistors with transparent oxide semiconductor ZnO serving as the electron channel and high-k $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ as the gate insulator. The devices exhibited low operation voltages (<4V) due to high capacitance of the $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ dielectric.

• 전자통신동향분석
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• 제35권2호
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• pp.69-78
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• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.577-580
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• 1999

High power density on-board power supply is implemented by using flat transformer. In the high frequency switching converters, large leakage inductance increases the switching stress and duty cycle loss, which sometimes limits maximum switching frequency. The flat transformer is designed by using special core structure, which has very low profile and low temperature rise since the thermal loading is spread evenly over a larger area. 100W, 3.3V output on board supply is built and tested and 50.7W/$\textrm{inch}^{3}$ power density is achieved.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.519-522
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• 2002

In this paper, we analyze the impact of plasma etching process induced device degradation on low temperature poly-Si TFTs. The results indicate the relationship between device degradation and PPID effect during plasma fabrication. The dual-gate structure, which is used to suppress leakage current, is also discussed in this research.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.655-658
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• 2007

Characteristics of Al cathode films deposited by using specially designed twin target sputter (TTS) system were investigated. It was found that Al cathode films prepared by TTS were amorphous structure with nanocrystallines due to low substrate temperature and OLEDs fabricated using TTS system have low leakage current density at reverse bias because of effective confinement of energetic particles during sputtering process.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제36회 동계학술대회 초록집
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• pp.171.2-171.2
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• 2009

• 한국진공학회:학술대회논문집
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• 한국진공학회 2008년도 제34회 동계학술대회 초록집
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• pp.315-315
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• 2008

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 추계학술발표강연 및 논문개요집
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• pp.70-70
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• 1998

• 한국세라믹학회지
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• 제41권6호
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• pp.464-470
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• 2004

ZnO-P $r_{6}$ $O_{11}$-CoO-C $r_2$ $O_3$- $Y_2$ $O_3$계 세라믹스로 구성된 ZPCCY계 바리스터의 소결시간별 DC 가속열화 스트레스에 대한 전기적 안정성을 조사하였다. 소결시간은 전기적 특성 및 안정성에 크게 영향을 미치는 것으로 나타났다. 소결시간이 증가함에 따라 비직선 지수는 51.2∼23.8의 범위로 감소하였으며, 누설전류는 1.3∼5.6 $\mu$A의 범위로 증가하였다. 1시간 소결된 바리스터는 비직선성은 우수하나 밀도가 낮은 관계로 안정성이 상대적으로 낮았으며, 3시간 소결된 바리스터는 안정성은 양호하나 비직선성이 다소 낮은 것으로 나타났다 2시간 소결된 바리스터는 비직선 지수가 38.6, 누설전류가 3.6 $\mu$A로 양호 하고, DC스트레스_0.95 $V_{1㎃}$15$0^{\circ}C$/12h에서 바리스터 전압, 비직선 지수, 누설전류, 손실계수 변화율이 각각 -0.8%, -1.8%, +74.4%, +0.9%를 나타냄으로서 안정성이 우수한 것으로 나타났다.다.