• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.4
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• pp.247-251
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• 2017

This paper proposes a low power transmission technique for single-carrier modulation with frequency domain equalization. As time domain signals and frequency domain signals have unique corresponding functions, inserting zeros after each symbol causes a repetition in other domain, so maximal ratio combining technique using repetitive transmission can be applied in the frequency domain. In this paper, we configure transmit signals to insert zeros after each symbols for single-carrier modulation with frequency domain equalization and maximal ratio receive combining block in the receiver structures, propose a structure for transmitter and receiver and show that its performance is better than the traditional algorithm by simulations.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.5
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• pp.892-897
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• 2007

This paper presents the output filter design and the output characteristic analysis by cut-off frequency set up of the LCR filter on NPC multi-level inverter with trap-filter. The single-phase NPC three-level inverter operates at low switching frequency. The proposed LC trap filter is comprised of a conventional LCR output filter, by using LC trap filter the need for high damping resistor and low LC cut-off frequency is eliminated. Also. low damping resistor is increased the output filter system. The multilevel inverter system used NPC type inverter in proper system for high power application and controller is used DSP(TMS320C31). The effectiveness of proposed system confirmed the validity through SPICE simulation and experimental results.

• Proceedings of the KOSOMBE Conference
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• v.1995 no.11
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• pp.109-112
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• 1995

This paper is a study on the detection of the significant point in ECG signal. ECG signal consists of two components; one is high frequency component to be detected and the other is low frequency component to be removed. AR model is appropriate for modelling and removing the low frequency component. AR model coefficients are updated by artificial neural network algorithm. We can remove the background noise(low frequency) by passing through the AR filter. The remaining signals which include high frequency noise are sent to the matched filter to pass only the signal which we want to extract. The template used in matched filter is updated adaptively.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.485-487
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• 2006

This paper describes a frequency synthesizer designed in a $0.25{\mu}m$ CMOS technology for using local oscillators for the IF stages. The design is focused mainly on low-power characteristics. A simple ring-oscillator based VCO is used, where a single control signal can be used for variable resistors. The designed PLL includes all building blocks for elimination of external components, other than the crystal, and its operating frequency can be programmed by external data. It operates in the frequency range of 250MHz to 800MHz and consumes l.08mA at 500MHz from a 2.5V supply. The measured phase noise is -85dBc/Hz in-band and -105dBc/Hz at 1MHz offset. The die area is $1.09mm^2$

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.209-210
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• 2006

Digital technology has been applied to marine seismic survey to develop data processing technology and multi-channel marine seismic survey. In result, high-resolution marine seismic survey ended in a success. Surveys are conducted for various purposes using various frequencies of acoustic sources. A low frequency source is used for deeper penetration and a high frequency source is used for higher resolution survey. In this study, a multi-source system was used for multi-channel marine seismic survey to acquire seismic sections of both low and high frequencies. Variations of depth of penetration and resolution would be used to achieve more accurate analysis of formations. In this study, the multi-source system consists of Bubble Pulser(400 Hz) for low frequency source and Sparker(1.5 kHz) for high frequency source.

• Language and Information
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• v.14 no.1
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• pp.145-163
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• 2010

This paper aims to propose that Benford's Law, non-uniform distribution of the leading digits in lists of numbers from many real-life sources, also appears in linguistic texts. The first digits in the frequency lists of morphemes from Sejong Morphologically Analyzed Corpora represent non-uniform distribution following Benford's Law, but showing complexity of numerical sources from complex systems like earthquakes. Benford's Law in texts is a principle reflecting regular distribution of low-frequency linguistic types, called LNRE(large number of rare events), and governing texts, corpora, or sample texts relatively independent of text sizes and the number of types. Although texts share a similar distribution pattern by Benford's Law, we can investigate non-uniform distribution slightly varied from text to text that provides useful applications to evaluate randomness of texts distribution focused on low-frequency types.

• Journal of Korea Society of Digital Industry and Information Management
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• v.11 no.4
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• pp.155-164
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• 2015

In this paper, we propose a new color interpolation method based on trilateral filter approach, which not only preserve the high-frequency components(image edge) while interpolating the missing raw data of color image(bayer data pattern), but also immune to the image noise components and better preserve the detail of the low-frequency components. The method is the trilateral filter approach applying a gradient to the low frequency components of the image signal in order to preserve the high-frequency components and the detail of the low-frequency components through the measure of the freedom of similarity among adjacent pixels. And also we perform Gaussian smoothing to the interpolated image data in order to robust to the noise. In this paper, we compare the conventional demosaicing algorithm and the proposed algorithm using 10 test images in terms of hue MAD, saturation MAD and CPSNR for the objective evaluation, and verify the performance of the proposed algorithm.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.53-58
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• 2013

In this paper, we proposed low power algorithm for battery residual capacity and a task. Algorithm the mobile devices power of the battery residual capacity for the task to perform power consumption to reduce the frequency alters. Task is different in power consumption according to kinds of in time accomplishment device to use. Adjustment of power consumption analyzes kinds of given tasks from having the minimum power consumption task to having the maximum power consumption task. Control frequency so that power consumption waste to be exposed to battery residual capacity can be happened according to the results analyzed. Experiment the frequency by adjusting power consumption a method to reduce using [7] and in the same environment power of the battery residual capacity consider the task to perform frequency were controlled. Efficiency was proved compare with the experiment results [7]. The experiments results show increment in the number of processing by 45.46% comparing with that [7] algorithm.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.