• Title/Summary/Keyword: low doping

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Comparison of Optical Properties of Ga-doped and Ag-doped ZnO Nanowire Measured at Low Temperature

  • Lee, Sang Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.15 no.5
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    • pp.262-264
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    • 2014
  • Pristine ZnO, 3 wt.% Ga-doped (3GZO) and 3 wt.% Ag-doped (3SZO) ZnO nanowires (NWs) were grown using the hot-walled pulse laser deposition (HW-PLD) technique. The doping of Ga and Ag in ZnO NWs was observed by analyzing the optical and chemical properties. We optimized the synthesis conditions, including processing temperature, time, gas flow, and distance between target and substrate for the growth of pristine and doped ZnO NWs. The diameter and length of pristine and doped ZnO NWs were controlled under 200 nm and several ${\mu}m$, respectively. Low temperature photoluminescence (PL) was performed to observe the optical property of doped NWs. We clearly observed the shift of the near band edge (NBE) emission by using low temperature PL. In the case of 3GZO and 3SZO NWs, the center photon energy of the NBE emissions shifted to low energy direction using the Burstein Moss effect. A strong donor-bound exciton peak was found in 3 GZO NWs, while an acceptor-bound exciton peak was found in 3SZO NWs. X-ray photoelectron spectroscopy (XPS) also indicated that the shift of binding energy was mainly attributed to the interaction between the metal ion and ZnO NWs.

Semiconductor Device with Ambipolar Transfer Characteristics (양방향성 전달특성을 갖는 반도체소자에 관한 연구)

  • Oh, Teresa
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2018.10a
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    • pp.193-194
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    • 2018
  • Common transistor has unipolar characteristics in accordance with the doping carriers and operation by the threshold voltage, which is related to the stability. It is required the low threshold voltage of transistors to increase the stability of devices. The sensing ability is about the detection of how low current, therefore there is difference between the low current and leakage current. This study researched the ambipolar characteristics of transistors with very low currents to define the difference between common n-type transistors with unipolar properties.

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AC Conductivity of $(Sr_{0.75}$,$La_{0.25}$) $TiO_3/SrTiO_3$ Superlattices

  • Choe, Ui-Yeong;Choe, Jae-Du;Lee, Jae-Chan
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2011.05a
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    • pp.31.2-31.2
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    • 2011
  • We have investigated frequency dependant conductivity (or permittivity) of low dimensional oxide structures represented by [($Sr_{0.75}$, $La_{0.25}$)$TiO_3$]$_1$/1$[SrTiO_3]_n$ superlattices. The low dimensional oxide superlattice was made by cumulative stacking of one unit cell thick La doped $SrTiO_3$ and $SrTiO_3$ with variable thickness from 1 to 6 unit cell, i,e, [($Sr_{0.75}$, $La_{0.25}$)$TiO_3$]$_1$/$[SrTiO_3]_n$ (n=1, 2, 3, 4, 5, 6). We found two kinds of relaxation when n is 3 and 4, while, inductance component was observed at n=1. This behavior can be explained by electron modulation in ($Sr_{0.75}$, $La_{0.25}$)$TiO_3/SrTiO_3$ superlattices. When n is 1, electrons by La doping well extend to un-doped layer. Therefore, the transport of superlattices follows bulk-like behavior. On the other hand, as n increased, the doped electrons became two types of carrier: one localized and the other extended. These results in two kinds of transport phase. At further increase of n, most of doped electrons are localized at the doped layer. This result shows that dimensionality of the oxide structure significantly affect the transport of oxide nanostructures.

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New Process Development for Hybrid Silicon Thin Film Transistor

  • Cho, Sung-Haeng;Choi, Yong-Mo;Jeong, Yu-Gwang;Kim, Hyung-Jun;Yang, Sung-Hoon;Song, Jun-Ho;Jeong, Chang-Oh;Kim, Shi-Yul
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.205-207
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    • 2008
  • The new process for hybrid silicon thin film transistor (TFT) using DPSS laser has been developed for realizing both low-temperature poly-Si (LTPS) TFT and a-Si:H TFT on the same substrate as a backplane of active matrix liquid crystal display. LTPS TFTs are integrated on the peripheral area of the panel for gate driver integrated circuit and a-Si:H TFTs are used as a switching device for pixel in the active area. The technology has been developed based on the current a-Si:H TFT fabrication process without introducing ion-doping and activation process and the field effect mobility of $4{\sim}5\;cm^2/V{\cdot}s$ and $0.5\;cm^2/V{\cdot}s$ for each TFT was obtained. The low power consumption, high reliability, and low photosensitivity are realized compared with amorphous silicon gate driver circuit and are demonstrated on the 14.1 inch WXGA+ ($1440{\times}900$) LCD Panel.

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Extraction of empirical formulas for electron and hole mobility in $In_{0.53}(Al_xGa_{1-x})_{0.47}As$ ($In_{0.53}(Al_xGa_{1-x})_{0.47}As$의 전자와 정공 이동도의 실험식 추출)

  • 이경락;황성범;송정근
    • Electrical & Electronic Materials
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    • v.9 no.6
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    • pp.564-571
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    • 1996
  • We calculated the drift-velocities of electrons and holes of I $n_{0.53}$(A $l_{x}$G $a_{1-x}$ )$_{0.47}$As, which is used for semiconductor materials of high performance HBTs, along with the various doping concentrations and Al mole fractions as well as the electric fields by Monte Carlo experiment. Especially, for the valence bands the accuracy of hole-drift-velocity was improved in the consideration of intervalley scattering due to the inelastic scattering of acoustic phonon. From the results the empirical formulas of the low- and high field mobility of electrons and holes were extracted by using nonlinear least square fitting method. The accuracy of the formulas was proved by comparing the formula of low-field electron mobility as well as drift-velocity of I $n_{0.53}$ G $a_{0.47}$As and of low-field hole mobility of GaAs with the measured values, where the error was below 10%. For the high-field mobilities of electron and hole the results calculated by the formulas were very well matched with the MC experimental results except at the narrow field range where the electrons produced the velocity overshoot and the corresponding error was about 30%.0%. 30%.0%.

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Low-Temperature Solution Process of Al-Doped ZnO Nanoflakes for Flexible Perovskite Solar Cells

  • Nam, SeongSik;Vu, Trung Kien;Le, Duc Thang;Oh, Ilwhan
    • Journal of Electrochemical Science and Technology
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    • v.9 no.2
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    • pp.118-125
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    • 2018
  • Herein we report on the selective synthesis and direct growth of nanostructures using an aqueous chemical growth route. Specifically, Al-doped ZnO (AZO) nanoflakes (NFs) are vertically grown on indium tin oxide (ITO) coated flexible polyethylene terephthalate (PET) sheets at low temperature and ambient environment. The morphological, optical, and electrical properties of the NFs are investigated as a function of the Al content. Furthermore, these AZO-NFs are integrated into perovskite solar devices as the electron transport layer (ETL) and the fabricated devices are tested for photovoltaic performance. It was determined that the doping of AZO-NFs significantly increases the performance metrics of the solar cells, mainly by increasing the short-circuit current of the devices. The observed enhancement is primarily attributed to the improved conductivity of the doped AZO-NF, which facilitates charge separation and reduces recombination. Further, our flexible solar cells fabricated through this low temperature process demonstrate an acceptable reproducibility and stability when exposed to a mechanical bending test.

Comparison of Drain-Induced-Barrier-Lowering (DIBL) Effect by Different Drain Engineering

  • Choi, Byoung-Seon;Choi, Pyung-Ho;Choi, Byoung-Deog
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.342-343
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    • 2012
  • We studied the Drain-Induced-Barrier-Lowering (DIBL) effect by different drain engineering. One other drain engineering is symmetric source-drain n-channel MOSFETs (SSD NMOSs), the other drain engineering is asymmetric source-drain n-channel MOSFETs (ASD NMOSs). Devices were fabricated using state of art 40 nm dynamic-random-access-memory (DRAM) technology. These devices have different modes which are deep drain junction mode in SSD NMOSs and shallow drain junction mode in ASD NMOSs. The shallow drain junction mode means that drain is only Lightly-Doped-Drain (LDD). The deep drain junction mode means that drain have same process with source. The threshold voltage gap between low drain voltage ($V_D$=0.05V) and high drain voltage ($V_D$=3V) is 0.088V in shallow drain junction mode and 0.615V in deep drain junction mode at $0.16{\mu}m$ of gate length. The DIBL coefficients are 26.5 mV/V in shallow drain junction mode and 205.7 mV/V in deep drain junction mode. These experimental results present that DIBL effect is higher in deep drain junction mode than shallow drain junction mode. These results are caused that ASD NMOSs have low drain doping level and low lateral electric field.

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Tunneling Current Calculation in HgCdTe Photodiode (HgCdTe 광 다이오드의 터널링 전류 계산)

  • 박장우;곽계달
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.29A no.9
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    • pp.56-64
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    • 1992
  • Because of a small bandgap energy, a high doping density, and a low operating temperature, the dark current in HgCdTe photodiode is almost composed of a tunneling current. The tunneling current is devided into an indirect tunneling current via traps and a band-to-band direct tunneling current. The indirect tunneling current dominates the dark current for a relatively high temperature and a low reverse bias and forward bias. For a low temperature and a high reverse bias the direct tunneling current dominates. In this paper, to verify the tunneling currents in HgCdTe photodiode, the new tunneling-recombination equation via trap is introduced and tunneling-recombination current is calculated. The new tunneling-recombination equation via trap have the same form as SRH (Shockley-Read-Hall) generation-recombination equation and the tunneling effect is included in recombination times in this equation. Chakrabory and Biswas's equation being introduced, band to band direct tunneling current are calculated. By using these equations, HgCdTe (mole fraction, 0.29 and 0.222) photodiodes are analyzed. Then the temperature dependence of the tunneling-recombination current via trap and band to band direct tunneling current are shown and it can be known what is dominant current according to the applied bias at athe special temperature.

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Rational Design of Binder-Free Fe-Doped CuCo(OH)2 Nanosheets for High-Performance Water Oxidation

  • Patil, Komal;Jang, Su Young;Kim, Jin Hyeok
    • Korean Journal of Materials Research
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    • v.32 no.5
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    • pp.237-242
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    • 2022
  • Designing and producing a low-cost, high-current-density electrode with good electrocatalytic activity for the oxygen evolution reaction (OER) is still a major challenge for the industrial hydrogen energy economy. In this study, nanostructured Fe-doped CuCo(OH)2 was discovered to be a precedent electrocatalyst for OER with low overpotential, low Tafel slope, good durability, and high electrochemically active surface sites at reduced mass loadings. Fe-doped CuCo(OH)2 nanosheets are made using a hydrothermal synthesis process. These nanosheets are clumped together to form a highly open hierarchical structure. When used as an electrocatalyst, the Fe-doped CuCo(OH)2 nanosheets required an overpotential of 260 mV to reach a current density of 50 mA cm-2. Also, it showed a small Tafel slope of 72.9 mV dec-1, and superior stability while catalyzing the generation of O2 continuously for 20 hours. The Fe-doped CuCo(OH)2 was found to have a large number of active sites which provide hierarchical and stable transfer routes for both electrolyte ions and electrons, resulting in exceptional OER performance.

Schottky barrier overlapping in short channel SB-MOSFETs (Short Channel SB-FETs의 Schottky 장벽 Overlapping)

  • Choi, Chang-Yong;Cho, Won-Ju;Chung, Hong-Bay;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.133-133
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    • 2008
  • Recently, as the down-scailing of field-effect transistor devices continues, Schottky-barrier field-effect transistors (SB-FETs) have attracted much attention as an alternative to conventional MOSFETs. SB-FETs have advantages over conventional devices, such as low parasitic source/drain resistance due to their metallic characteristics, low temperature processing for source/drain formation and physical scalability to the sub-10nm regime. The good scalability of SB-FETs is due to their metallic characteristics of source/drain, which leads to the low resistance and the atomically abrupt junctions at metal (silicide)-silicon interface. Nevertheless, some reports show that SB-FETs suffer from short channel effect (SCE) that would cause severe problems in the sub 20nm regime.[Ouyang et al. IEEE Trans. Electron Devices 53, 8, 1732 (2007)] Because source/drain barriers induce a depletion region, it is possible that the barriers are overlapped in short channel SB-FETs. In order to analyze the SCE of SB-FETs, we carried out systematic studies on the Schottky barrier overlapping in short channel SB-FETs using a SILVACO ATLAS numerical simulator. We have investigated the variation of surface channel band profiles depending on the doping, barrier height and the effective channel length using 2D simulation. Because the source/drain depletion regions start to be overlapped each other in the condition of the $L_{ch}$~80nm with $N_D{\sim}1\times10^{18}cm^{-3}$ and $\phi_{Bn}$ $\approx$ 0.6eV, the band profile varies as the decrease of effective channel length $L_{ch}$. With the $L_{ch}$~80nm as a starting point, the built-in potential of source/drain schottky contacts gradually decreases as the decrease of $L_{ch}$, then the conduction and valence band edges are consequently flattened at $L_{ch}$~5nm. These results may allow us to understand the performance related interdependent parameters in nanoscale SB-FETs such as channel length, the barrier height and channel doping.

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