• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.166-166
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• 2006

The photoluminescence (PL) efficiency of $Ir(ppy)_{3}$:PVK is lower than $Ir(ppy)_{3}$:CBP for the whole range of doping concentration and this low PL efficiency can be a reason of the lower efficiency of PhPLED than PhOLED. The lower efficiency is originated from the large bi-excitonic quenching such as the triplet-triplet annihilation. The PhPLEDs showed very short lifetime. The short lifetime was found to be originated from the instability of the doubly reduced $Ir(ppy)_{3^{-2}}$. The double reduction takes place because of the low electron mobility of PVK and large energy difference of LUMO level between PVK and $Ir(ppy)_{3}$.

• Journal of the Korean Ceramic Society
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• v.37 no.6
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• pp.524-529
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• 2000

Silica slab wavegudie was fabricated on Si substrates by FHD for planar optical passive devices. The slab waveguide consists of lower clad and core layers, where core layer index is controlled by GeO2 addition. Doping of GeO2 in silica is difficult because of the low deposition density due to nonspherical particle generation in FHD process. Silica core particles deposited at various conditions such as flame temperature and substrate scanning were analyzed by SEM and TEM. As the flame temperature increased, the surface roughness of the core layer was decreased up to 3.6 nm after consolidation. Index difference and thickness of core of slab waveguide were 0.3%, 8$\mu\textrm{m}$ respectively. Measured optical loss at TE mode was <0.04 dB/cm at 1.3$\mu\textrm{m}$ and <0.06 dB/cm at 1.55$\mu\textrm{m}$.

• ETRI Journal
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• v.25 no.4
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• pp.247-252
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• 2003

This paper presents results from experiments on laser-annealed SiGe-selective epitaxial growth (LA-SiGe-SEG). The SiGe-SEG technology is attractive for devices that require a low band gap and high mobility. However, it is difficult to make such devices because the SiGe and the highly doped region in the SiGe layer limit the thermal budget. This results in leakage and transient enhanced diffusion. To solve these problems, we grew in situ doped SiGe SEG film and annealed it on an XMR5121 high power XeCl excimer laser system. We successfully demonstrated this LA-SiGe-SEG technique with highly doped Ge and an ultra shallow junction on p-type Si (100). Analyzing the doping profiles of phosphorus, Ge compositions, surface morphology, and electric characteristics, we confirmed that the LA-SiGe-SEG technology is suitable for fabricating high-speed, low-power devices.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.2
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• pp.235-238
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• 2008

This paper explores 28 nm MOSFET design for LSTP(Low Standby Power) applications using TCAD(Technology Computer Aided Design) simulation. Simulated results show that the leakage current of the MOSFET is increasingly dominated by GIDL(Gate Induced Drain Leakage) instead of a subthreshold leakage as the Source/Drain extension doping increases. The GIDL current can be reduced by grading lateral abruptness of the drain at the expense of a higher Source/Drain series resistance. For 28 nm MOSFET suggested in ITRS, we have shown Source/Drain design becomes even more critical to meet both leakage current and performance requirement.

• 한국초전도학회:학술대회논문집
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• 2009.07a
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• pp.10-10
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• 2009

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.449-452
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• 2010

We have analyzed channel doping and dimensions(channel length, width and thickness) for the optimum subthreshold characteristics of DG(Double Gate) MOSFET based on the model of MicroTec 4.0. Since the DGMOSFET is the candidate device to shrink short channel effects, the determination of design rule for DGMOSFET is very important to develop sub-100nm devices for high speed and low power consumption. As device size scaled down, the controllability of dimensions and oxide thickness is very low. We have analyzed the short channel effects for the variation of channel dimensions, and found the design conditions of DGMOSFET having the optimum subthreshold characteristics for digital applications.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.435-438
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• 2007

$V_{2}O_{5}$ was tested as a p-dopant for lower operating voltage and higher stability of OLEDs. Low voltage and high stability were achieved using this doping layer. It can be separated to bulk and interface contributions and the latter is a more dominant factor both of operation voltage and stability.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.2
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• pp.249-255
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• 1996

A self-aligned latch-up suppressed IGBT has been proposed and the process method and the device characteristics of the IGBT have been verified by numerical simulation. As the source is laterally diffused through the sidewall of the trench in the middle of the body, the size of the source is small and the doping concentration of the source is lower than that of the p++ body and the emitter efficiency of the parasitic npn transistor is low so that latch-up may be suppressed. No additional mask steps for p++ region, source, and source contact are required so that small sized body can be obtained Latch-u current density higher than 10000 A/cm$^{2}$ have been achieved by adjusting the process conditions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.125-130
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• 2000

Two step growth of reduced pressure chemical vapor eposition has been successfully developed to achieve in-situ phosphorus-doped silicon epilayers, and the characteristic evolution on their microstructures has been investigated using scanning electron microscopy, transmission electron microscopy, and secondary ion mass spectroscopy. The two step growth, which employs heavily in-situ P doped silicon buffer layer grown at low temperature, proposes crucial advantages in manipulating crystal structures of in-situ phosphorus doped silicon. In particular, our experimental results showed that with annealing of the heavily P doped silicon buffer layers, high-quality epitaxial silicon layers grew on it. the heavily doped phosphorus in buffer layers introduces into native oxide and plays an important role in promoting the dispersion of native oxides. Furthermore, the phosphorus doping concentration remains uniform depth distribution in high quality single crystalline Si films obtained by the two step growth.

• Bulletin of the Korean Chemical Society
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• v.20 no.3
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• pp.333-336
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• 1999

The polyaniline films with various insoluble parts are fabricated. The oxidation state (1-y) of these polyaniline is 0.53 and 0.54, respectively. To control the interchain and intrachain interaction of the polymer, the polyaniline films are stretched with appropriate ratio. The insoluble part of polyaniline synthesized at room temperature (low molecular weight) is 12%-76% and that of polyaniline synthesized at 0 'IC (intermediate molecular weight) is 65%-89%. The low molecular weight polyaniline films with various drawing ratios have amorphous structure. In the intermediate weight polyaniline films, the crystallinity of films increases with drawing ratio as well as insoluble part. The difference of the insoluble part affects electrical conductivity which is increased dramatically with draw ratio. In particular, the higher insoluble part caused greater increase in electrical conductivity.