• Information and Communications Magazine
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• v.11 no.8
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• pp.60-77
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• 1994

This paper presents a survey of video coding schemes which use wavelet transform for the videophone on very low bit rate commun ication chan nel( ego 10 Kbps Public Service Telephone Network). Firstly, we introduce the standardization efforts to make the low bit rate videophone architecture and the typical application of low bit rate video coding scheme. Secondly, we summarize the several requirements on videophone, delay, encoder/decoder complexity, low bitrate, and progressive transmission capability. Third, we review the basic theory of wavelet transform without much mathematics. We compare the wavelet transform with short-time fourier transform and subband filters. Fourth, we summarize the video coding schemes proposed so far, and evaluate them with Ule requirements. Lastly, we conclude with fu¬ture research directions.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.5
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• pp.46-54
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• 2011

In this paper, we propose a low-complexity loop filtering method depending on transform-block regions. Block adaptive loop filter (BALF) was developed to improve about 10% in compression performance for the next generation video coding. The BALF employs the Wiener filter that makes reconstructed frames close to the original ones and transmits filter-related information. However, the BALF requires high computational complexity, while it can achieve high compression performance because the block adaptive loop filter is applied to all the pixels in blocks. The proposed method is a new loop filter that classifies pixels in a block into inner and boundary regions based on the characteristics of the integer transform and derives optimum filters for each region. Then, it applies the selected filters for the inner and/or boundary regions. The decoder complexity can be adjusted by selecting region-dependent filter to be used in the decoder side. We found that the proposed algorithm can reduce 35.5% of computational complexity with 2.56% of compression loss, in case that only boundary filter is used.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.143-146
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• 2009

In this paper, we investigated the list sphere decoders (LSD) for multiple-input multiple-output (MIMO) systems. We showed that the ordering procedures play an important role in LSD in order to achieve the low complexity without degrading the bit-error-rate (BER) performance. Then, we proposed a novel ordering algorithm for the LSD which uses a look-up table and simply comparative operations. Comparative results in terms of BER performance and computational complexity are provided through computer simulations.

• Proceedings of the Korea Contents Association Conference
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• 2006.11a
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• pp.499-502
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• 2006

H.264/MPEG4 Advanced Video coding joint standard needs deblocking filter of decoder. We propose a better deblocking algorithm ensuring picture quality even if it is low bit-rate and bandwidth in MPEG-4 video. The complexity diminishes in proposed deblocking algorithm because it uses only simple shift, addition and comparison. We handle dividing into complexity area, medium area and simple area after counting boundary intensity of mask block to identify presence of block effects. As a result of experiment, we make certain of that block effects reduces in proposed deblocking algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.4
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• pp.1987-2001
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• 2017

Low-density parity-check (LDPC) codes have attracted a great attention because of their excellent error correction capability with reasonably low decoding complexity. Among decoding algorithms for LDPC codes, the min-sum (MS) algorithm and its modified versions have been widely adopted due to their high efficiency in hardware implementation. In this paper, a self-adaptive MS algorithm using the difference of the first two minima is proposed for faster decoding speed and lower power consumption. Finding the first two minima is an important operation when MS-based LDPC decoders are implemented in hardware, and the found minima are often compressed using the difference of the two values to reduce interconnection complexity and memory usage. It is found that, when these difference values are bounded, decoding is not successfully terminated. Thus, the proposed method dynamically decides whether the termination-checking step will be carried out based on the difference in the two found minima. The simulation results show that the decoding speed is improved by 7%, and the power consumption is reduced by 16.34% by skipping unnecessary steps in the unsuccessful iteration without any loss in error correction performance. In addition, the synthesis results show that the hardware overhead for the proposed method is negligible.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.148-154
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• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard are required a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithm for LDPC codes. First, sequential decoding with partial group is proposed. It has same H/W complexity, and fewer number of iteration's are required at same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method is reduced number of unnecessary iteration. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.3
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• pp.23-31
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• 2010

The increasing demands on low-power, and low-complexity video encoder have been motivating extensive research activities on distributed video coding (DVC) in which the encoder compresses frames without utilizing inter-frame statistical correlation. In DVC encoder, contrary to the conventional video encoder, an error control code compresses the video frames by representing the frames in the form of syndrome bits. In the meantime, the DVC decoder generates side information which is modeled as a noisy version of the original video frames, and a decoder of the error-control code corrects the errors in the side information with the syndrome bits. The noisy observation, i.e., the side information can be understood as the output of a virtual channel corresponding to the orignal video frames, and the conditional probability of the virtual channel model is assumed to follow a Laplacian distribution. Thus, performance improvement of DVC systems depends on performances of the error-control code and the optimal reconstruction step in the DVC decoder. In turn, the performances of two constituent blocks are directly related to a better estimation of the parameter of the correlation channel. In this paper, we propose an algorithm to estimate the parameter of the correlation channel and also a low-complexity version of the proposed algorithm. In particular, the proposed algorithm minimizes squared-error of the Laplacian probability distribution and the empirical observations. Finally, we show that the conventional algorithm can be improved by adopting a confidential window. The proposed algorithm results in PSNR gain up to 1.8 dB and 1.1 dB on Mother and Foreman video sequences, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.93-96
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decode. is parameterized for the code rates 1/2, 1/3 and constraint lengths 7, 9, thus it has four operation modes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.1-8
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• 2004

This paper proposes a novel algorithm for a low power turbo decoder based on reduction of number of decoding iterations, targeting power-critical mobile communication devices. Previous researches that attempt to reduce number of decoding iterations, such as CRC-aided and LLR methods, either show degraded BER performance in return for reduced complexity or require additional hardware resources for controlling the number of iterations to meet BER performance, respectively. The proposed algorithm can reduce power consumption without degrading the BER performance, and it is achieved with minimal hardware overhead. The proposed algorithm achieves this by comparing consecutive hard decision results using a simple buffer and counter. Simulation results show that the number of decoding iterations can be reduced to about 60% without degrading the BER performance in the proposed decoder, and power consumption can be saved in proportion to the number of decoding iterations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.