• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2001.11a
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• pp.157-160
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• 2001

본 논문에서 5.8GHz의 주파수 대역에서 사용할 수 있는 향상된 커플링 구조와 크기를 줄인 dual-mode microstrip bandpass filter를 설계하였다. 여기서 meander loop resonator를 쓰는 이유는 크기가 작고 방사 손실이 적으며 패턴이 간단하기 때문이다. 또한 이와 비슷한 특성을 갖는 ring, square patch, disk등은 불연속 성분을 가짐으로써 이중모드의 구현이 가능하다. 향상된 형태의 dual-mode microstrip bandpass filter의 변형된 T-shaped meander loop resonator를 소형으로 발전되고. 높은 선택도를 가지는 구조이다. 이 형태의 filter에서 150MHz의 bandwidth을 가지고 5.8GHz주파수를 가지는 구조로 설계하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.376-380
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• 1987

The closed-loop transfer function of 2-nd order PLL (phase-looked loop)of which loop filter has active-lag 1-st order is found. Considering the three criteria of system performance: the transient response time of the circuit, noise bandwidth by the linear analysis and stability which uses root-locus method, the optimum value of damping factor is 1.0 and the natural frequency which depends upon the signal frequency can be determined after consideration of the trade-off relationship between the transient response time and the noise bandwidth.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1836-1840
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• 2003

This paper, we propose a new phase-locked loop (PLL) system with the controllable output phase, independent from the output frequency, and lock-up time. This PLL system has a dual control loop is described, the inner loop greatly improved VCO characteristic such as faster speed response as well as higher operation bandwidth, to minimize the effect of the VCO noise and the power supply variation and also get better linearity of VCO output. The main loop is the heart of this PLL which greatly improved the output frequency instability due to the external high frequency noise coupling to the input reference frequency also the main loop can control the output phase, independent from the output frequency, and reduce the lock-up time of the step frequency response. The experimental results confirm the validity of the proposed strategy.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.42-50
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• 1984

The method of increasing the bandwidth of distributed amplifier by the feedback loop is presented in this paper. In this method, it is tried to increase the gain of the amplifier in the high frequency range by giving a positive feedback on the device, while giving no influence in the low frequency range. For the simplicity of the amplifier design the transmission line theory of periodical structure with a unilateral divice is used in the design, and the 2-ports cascade network theory developed by K.B. Niclas is used in computer analysis for the purpose of precise results. In this simulation, the bandwidth of the amplifier is increased from 16 [GHz] without feedback loop to about 20 [GHz] with the feedback loop.

• Proceedings of the KSR Conference
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• 2003.05a
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• pp.487-492
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• 2003

This paper designs a Korea train identification module using a RFID system. Frequency bandwidth transmits and receives messages using the 27.095Mhz and 4.234Mhz in the ISM bandwidth. The mode of the modulation uses a transmission ASK and a receiving FSK. And it uses a reader and transponder using an active transponder. We use the loop antenna which the antenna has the directional.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.1
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• pp.56-62
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• 2011

A Satellite transponder is mounted on the Satellite and performs radio communications with the ground station. A Digital transponder compared to The analog transponder is made easy and accurate performance prediction. Also Modulation Scheme, Data Rate, Loop Bandwidth, Modulation Index and etc. can be changed on orbit, by implementing FPGA can reduce the weight and volume. The core technology of digital transponder is Carrier Recovery loop. Dynamic Range, Frequency Tracking Range, Frequency Tracking Rate and Coherent performance are determined by the performance of the Carrier Recovery loop. In this paper, we proposed the structure of Carrier Recovery loop for the Satellite digital transponder, then tested and verified the structure.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.12 no.1
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• pp.58-65
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• 2013

It's introduced a BLA(Branch Loop Antenna) that is modified from conventional loop, and verified antenna performances for applying to mobile handset. Branch elements are added to a rectangular loop, and low resonance is obtained by the length of the branch line. When resonance frequency of a single loop is 2.5GHz, BLA had near 900 MHz under the same antenna size. Multiple resonances are established by the locations of branch connection and their lengths. By the implementation and measurement for the dual band BLA, it's showed 75MHz -10dB bandwidth and -3.03~-1.46dBi average gains with 49.73~71.39% efficiencies at GSM900 band, and 90MHz -6dB bandwidth and -8.14~-2.17dBi average gains with 15.34~60.62% efficiencies at DCS1900 band. And H-plane radiation patterns were omni-directional. These performances are good for the mobile handset antenna.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.685-692
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• 2008

In this paper, we propose a timing recovery loop for Inmarsat mini-m system downlink receiver. Inmarsat mini-m system requires a timing recovery loop which is robust in frequency offset and has fast acquisition because Inmarsat mini-m system specification requires frequency tolerance is required of ${\pm}924$ Hz (signal bandwidth: 2.4 kHz) and acquisition time of UW (Unique Word) signal duration (15ms).Therefore, we propose a timing recovery loop which is suitable for Inmarsat mini-m system. The proposed timing recovery loop adopted noncoherent UW detector and differential ELD which applied differential UW signal for stability and fast acquisition in frequency offset environment. Simulation results show that the proposed timing recovery loop has stable operation and fast acquisition in frequency offset environment for the system.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.277-280
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• 2001

The proposed clock generator lowers the operating frequency in a system core though it keeps data bandwidth high because it has a multiphase clocking architecture. Moreover. it has a dual loop which is comprised of an inner analog phase generation loop and outer digital phase control loop. It has both advantages of DLL's wide operating range and DLL's low jitter The proposed design has been demonstrated in terms of the concept and Hspice simulation. All circuits were designed using a 0.25${\mu}{\textrm}{m}$ CMOS process and simulated with 2.5 V power supply.

• Journal of information and communication convergence engineering
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• v.8 no.5
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• pp.489-492
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• 2010

This paper proposes the planar-type modified monopole antennas of loop structure. This antenna has an opened center of a conventional closed loop structure with an inside-folded terminal of the loop microstrip line. The size of the proposed antenna was minimized by folding the end of the loop. Also, the reactance value has been minimized by increasing capacitances between the coupled microstrip line. Therefore the proposed antenna has been compacted to about 20% from a conventional loop antenna and has increased its efficiency. The proposed antennas have an omni-directional pattern, the antenna gain was 3.67 [dBi] and the bandwidth was 900 MHz (2.6~3.56 GHz) with VSWR$\leq$2 from the simulated and the measured results. The frequency utilization coefficient was 29.9%. These properties could satisfy the S-DMB band.