• 대한인간공학회:학술대회논문집
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• 대한인간공학회 1996년도 춘계학술대회논문집
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• pp.113-127
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• 1996

In Human Reliability Analysis(HRA), the uncertainties involved in many factors that affect human reliability have to be represented as the quantitative forms. Conventional probability- based human reliability theory is used to evaluate the effect of those uncertainties but it is pointed out that the actual human reliability should be different from that of conventional one. Conventional HRA makes use of error rates, however, it is difficult to collect data enough to estimate these error rates, and the estimates of error rates are dependent only on engineering judgement. In this paper, the error possibility that is proposed by Onisawa is used to represent human reliability, and the error possibility is obtained by use of fuzzy reasoning that plays an important role to clarify the relation between human reliability and human error. Also, assuming these factors are connected to the top event through Fault Tree structure, the influence and correlation of these factors are measured by fuzzy operation. When a fuzzy operation is applied to Fault Tree Analysis, it is possible to simplify the operation applying the logic disjuction and logic conjuction to structure function, and the structure of human reliability can be represented as membership function of the top event. Also, on the basis of the the membership function, the characteristics of human reliability can be evaluated by use of the concept of pattern recognition.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 2005년도 추계학술발표회
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• pp.991-992
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• 2005

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.393-393
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• 2000

FTA(Fault Tree Analysis) is a safety analysis method that focuses on one particular accident or main system failure and provides a method of determining causes of that event. While most of the statistical and cut set analysis have been automated, actual construction of the fault-tree is usually done manually. Manual construction of the fault-tree is extremely time consuming and it requires high level of expertise and experience. In addition to the time involved, different analyst often produces different fault-trees either by incorrect logic or omission of certain events. Automatic fault-tree construction system can be efficient in solving above problems. This study presents a new Digraph-FT conversion algorithm that leads automatic FTA system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
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• pp.615-617
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• 2000

Temporal Logic Frameworks is convenient to represent temporal relation. It is useful to represent a dynamic properties of Discrete Event Dynamic Systems. Also, it is convenient to express a current and next state of event using logical representation. Because the teachability tree of the Temporal Logic Frameworks is very complexity it is difficult to understand. In this paper, we defined some rules to represent Temporal Logic Frameworks by Petri Net and proposed am method of the representation of them Petri Net for the Temporal Logic Frameworks. An example are used to demonstrate the feasibility of this method.

• 전자공학회논문지A
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• 제33A권6호
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• pp.206-219
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• 1996

This paper describes a data structure and evaluation algorithm to improve the perofmrances MOS logic-with-timing simulation in computation and accuracy. In order to efficiently simulate the logic and timing of driver-load networks, (1) a tree data structure to represent the mutual interconnection topology of switches and nodes in the driver-lod network, and (2) an algebraic modeling to efficiently deal with the new represetnation, (3) an evaluation algorithm to compute the linear resistive and capacitive behavior with the new modeling of driver-load networks are developed. The higher modeling presented here supports the structural and functional compatibility with the linear switch-level to simulate the logic-with-timing of digital MOS circuits at a mixed-level. This research attempts to integrate the new approach into the existing simulator RSIM, which yield a mixed-klevel logic-with-timing simulator MIXIM. The experimental results show that (1) MIXIM is a far superior to RSIM in computation speed and timing accuracy; and notably (2) th etiming simulation for driver-load netowrks produces the accuracy ranged within 17% with respect ot the analog simulator SPICE.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제8권2호
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• pp.121-125
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• 2008

It is essential to maintain hierarchical information properly for efficient XML query processing. Well known approach to represent hierarchical information of XML tree is assigning a specific node number to each node of XML tree. Insertion and deletion of XML node can occur at any position in a dynamic XML tree. A dynamic numbering scheme allows us to add nodes to or delete nodes from an XML tree without relabeling or with relabeling only a few existing nodes of XML tree while executing XML query efficiently. According to W3C XQuery update facility specifications a node can be added as first or last child of the existing node in XML tree. Generating new number for last child requires referencing the number of previous last child. Getting the number of last child is very costly with previous approaches. We have developed a new dynamic numbering scheme PSN which is very effective for insertion of a node as last child. Our approach reduces the time to find last child dramatically by removing sorting of children.

• 대한전자공학회논문지SD
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• 제44권2호
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• pp.104-112
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• 2007

본 논문에서는 저온 다결정 실리콘 공정에서 얻어지는 박막트랜지스터를 이용하여 $7{\times}7$ 병렬처리 곱셈기를 설계하였다. 7개의 부분곱은 Folding 회로를 기본으로 설계된 다치 논리 회로(7-3 Compressor)와 3-2 Compressor를 통해 2비트로 출력되어 Carry Propagating Adder로 전달되는 구조를 통해 Carry전달 지연을 최소화하여 연산속도를 향상시켰다. 그리고 전류모드로 동작하는 곱셈기에서 사용되는 전류원을 부분적으로 차단함으로써 전력소모를 감소시켰다. HSPICE 시뮬레이션 과정을 통해 제안된 곱셈기는 Wallace Tree 곱셈기에 비해 PDP(Power Delay Product)가 23%, EDP(Energy Delay Product)가 59%, 연산 속도가 47% 향상됨을 확인하였다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제4권1호
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• pp.34-39
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• 2004

Huffman coding which has been used in many data compression algorithms is a popular data compression technique used to reduce statistical redundancy of a signal. It has been proposed that the Huffman algorithm can decode efficiently using characteristics of the Huffman tables and patterns of the Huffman codeword. We propose a new Huffman decoding algorithm which used a multi way tree search and present an efficient hardware implementation method. This algorithm has a small logic area and memory space and is optimized for high speed decoding. The proposed Huffman decoding algorithm can be applied for many multimedia systems such as MPEG audio decoder.

• 시스템엔지니어링학술지
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• 제12권1호
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• pp.41-58
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• 2016

Reliability Centered Maintenance (RCM) introduces a systematic method and decision logic tree for utilizing previous operating experience focused on reliability and optimization of maintenance activities. In this paper RCM methodology is applied on safety injection system for APR-1400. Functional Failure Mode Effects and Criticality Analysis (FME&CA) are applied to evaluate the failure modes and the effect on the component, system and plant. Logic Tree Analysis (LTA) is used to determine the optimum maintenance tasks. The results show that increasing the condition based maintenance will reduce component failure and improve reliability and availability of the system. Also the extension of the surveillance test interval of Safety Injection Pumps (SIPs) would lead to an improved pump's availability, eliminate the unnecessary maintenance tasks and this will optimize maintenance activities.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1492-1494
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• 1987

This paper describes a hardware architecture called Edge Painting Machine for real time generation of scan line images for raster scan graphics display. The Edge Painting Machine consists of Scanline Processor which converts polygon data sorted in their depth priority into a set of scan line commands for each scan line, and Edge Painting Tree which converts the scanline commands set into a raster line image. Edge painting tree has been designed using combinational logic circuit. The designed circuit has been simulated to verify the proper functioning. A salient feature of the EPT is that hardware composition is simple, because each processor is constituted by only combinational logic circuit.