• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.12
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• pp.1484-1493
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• 1992

In this paper, we propose the polarization coding of optical logic gates using filters and LCTV's, and represent the real-time system of an optical parallel adder to improve a carry propagation delay time. We fabricated a polarization filter for the polarization coding of a cell and an electrical system instead of an optical flip-flop which was necessary to an optical parallel adder. We used an optical fiber to play a part of decoding mask and interconnections in an optical parallel adder. The experimental results show that the polarization coding of a cell can represent 16 optical logic functions and that the implemented optical parallel adder can operate in real-time.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.1-11
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• 1997

We developed a base station modulator ASIC for CDMA digital cellular system. In CDMA digital cellular system, the modulation is performed by convolutional encoding and QPSK with spread spectrum. The function blocks of base station modulator are CRC, convolutional encoder, interleaver pseudo-moise scrambler, power control bit puncturing, walsh cover, QPSK, gain controller, combiner and multiplexer. Each function block was designed by the logic synthesis of VHDL codes. The VHDL code was described at register transfer level and the size of code is about 8,000 lines. The circuit simulation and logic simulation were performed by COMPASS tools. The chip (ES-C2212B CMB) contains 25,205 gates and 3 Kbit SRAM, and its chip size is 5.25 mm * 5,45 mm in 0.8 mm CMOS cell-based design technology. It is packaged in 68 pin PLCC and the power dissipation at 10MHz is 300 mW at 5V. The ASIC has been fully tested and successfully working on the CDMA base station system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.2
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• pp.47-54
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• 1982

In this paper, a improved per-channel PCM Coder with 1-bit interpolation is proposed. The coder converts a telephone signal to 15-segments u-law PCM signal of a large dynamic range. The A/D conversion technique of the proposed converter requires a feedback loop around a quantizer operates at high speed, and a accumulater for accumulating the quantized values to provide PCM outputs. To obtain both linear and compressed PCM signals a improved table look-up method is presented. The operations of the proposed converter are certified through the experiments to be good. The experimental circuit comprises TTL logic gates, a resistive D/Z converter and a simple differential amplifier. From the results of the experiments, it is known that the proposed converter has many advantage to be adopted economically for per-channel onverter used in rural area service.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.3
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• pp.115-122
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• 1985

In this paper, A decoder for the product of the (7, 4) cyclic code and the (3, 1) cyclic code was designed with less majority gates than other ordinary two-step majority-logic decoder using the same codes, then it was constucted in simple sturucture as a result of the use of a ROM as a mojority gate. It took 42 clock pulses to correct a received word(or 21bits) entirely. And so the decoding time in this decoding was multiplied by a factor of about 0.7 relative to the decoding time in the previous decoding in which two decoders and two-demensional word arrays were used together.

• Korean Journal of Optics and Photonics
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• v.13 no.5
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• pp.421-424
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• 2002

By using SOA (Semiconductor Optical Amplifier) based devices, an all-optical half adder has been successfully demonstrated at 10 Gb/s. All-optical XOR and AND gates are utilized to realize SUM and CARRY. Since SUM and CARRY have been simultaneously realized to form the all-optical half adder, complex calculation and signal processing can be achieved.

• Journal of the Korea Society of Computer and Information
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• v.19 no.12
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• pp.369-384
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• 2014

Since the start of gifted education in 2002, educational support system has now been established, and sufficient growth in quantitative aspects has been achieved in Korea. On the other hand, they report that there are insufficient points in terms of education quality. In other words, most of the gifted education simply expands knowledge by prior-learning. In order to improve the quality of gifted education, they should enhance critical-thinking and creativity able to apply interdisciplinary principles or phenomena for solving problems. In this study, we designed and developed a convergent teaching-learning materials based on the concept of integrated education, which explore the process that basic logic operations such as AND, OR, XOR do the role of computer cells. A survey result showed that student satisfaction(usefulness, understanding, interest) of the materials is significantly higher than that of other traditional learning topics, and the design intent was met.

• Interdisciplinary Bio Central
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• v.4 no.3
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• pp.10.1-10.12
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• 2012

Introduction: We investigated frameshift suppressor tRNAs previously reported to use five-base anticodon-codon interactions in order to provide a collection of frameshift suppressor tRNAs to the synthetic biology community and to develop modular frameshift suppressor logic devices for use in synthetic biology applications. Results and Discussion: We adapted eleven previously described frameshift suppressor tRNAs to the BioBrick cloning format, and built three genetic logic circuits to detect frameshift suppression. The three circuits employed three different mechanisms: direct frameshift suppression of reporter gene mutations, frameshift suppression leading to positive feedback via quorum sensing, and enzymatic amplification of frameshift suppression signals. In the course of testing frameshift suppressor logic, we uncovered unexpected behavior in the frameshift suppressor tRNAs. The results led us to posit a four-base binding hypothesis for the frameshift suppressor tRNA interactions with mRNA as an alternative to the published five-base binding model. Conclusion and Prospects: The published five-base anticodon/codon rule explained only 17 of the 58 frameshift suppression experiments we conducted. Our deduced four-base binding rule successfully explained 56 out of our 58 frameshift suppression results. In the process of applying biological knowledge about frameshift suppressor tRNAs to the engineering application of frameshift suppressor logic, we discovered new biological knowledge. This knowledge leads to a redesign of the original engineering application and encourages new ones. Our study reinforces the concept that synthetic biology is often a winding path from science to engineering and back again; scientific investigations spark engineering applications, the implementation of which suggests new scientific investigations.

• ETRI Journal
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• v.26 no.6
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• pp.555-559
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• 2004

We propose an efficient digital IF down converter architecture for dual-mode WCDMA/cdma2000 based on the concept of software defined radio. Multi-rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual-mode receiver for WCDMA and cdma2000. A sub-sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi-rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.

• ETRI Journal
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• v.24 no.6
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• pp.473-476
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• 2002

This letter proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit designs using don't-care sets. The proposed algorithm decreases power dissipation by partitioning a given circuit using a kernel extracted from the logic. The proposed algorithm also reduces the area overhead by minimizing duplicated gates in the partitioned sub-circuits. The partitioned subcircuits are further optimized utilizing observability don't-care sets. Experimental results for the MCNC benchmarks show that the proposed algorithm synthesizes circuits that on the average consume 22.5% less power and have 12.7% less area than circuits generated by previous algorithms based on a precomputation scheme.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.238-241
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• 2000

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA. (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL models. We have peformed logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5 $\mu\textrm{m}$ standard cell library (STD80). The total number of gates is about 130,000.