• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Journal of the Society of Naval Architects of Korea
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• v.43 no.3 s.147
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• pp.322-330
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• 2006

Numerical calculations are carried out for flow past a circular cylinder forced oscillating normal to the free-stream flow at a fixed Reynolds number equal to 185. The cylinder oscillation frequency ranged from 0.8 to 1.2 of the natural vortex-shedding frequency, and the oscillation amplitude extended up to 20% of the cylinder diameter. IBM (Immersed Boundary Method) with direct momentum forcing was adopted to handle both of a stationary and an oscillating cylinder Present results such as time histories of drag and lift coefficients for both stationary and oscillating cases are in good agreement with previous numerical and experimental results. The instantaneous wake patterns of oscillating cylinder with different oscillating frequency ratios showed the synchronized wakes pattern in the lock-in region and vortex switching phenomenon at higher frequency ratio than the critical frequency ratio.

• Journal of IKEEE
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• v.21 no.4
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• pp.416-419
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• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.1
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• pp.107-111
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• 2013

The gyroscopes have been used as a suitable inertial instrument for the navigation guidance and attitude controls. The accuracy as very sensitive sensor is limited by the lock-in region (dead band) due to the frequency coupling between two counter-propagating waves at low rotation rates. This frequency coupling gives no phase difference, and an angular increment is not detected. This problem can be overcome by mechanically dithering the gyroscope. This paper presents the design method of mechanical dither by the theoretical considerations and the verification of the theoretical equations through FEM applications. As a result, comparing to the past result, the maximum prediction error of resonant frequency was within 3 percent and peak dither rate was within 5 percent. It was found that the theoretical equations can be feasible for the mechanical performance of dither.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.37 no.5
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• pp.502-510
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• 2009

Laser Inertial Navigation System(LINS) consists of Ring Laser Gyroscopes(RLG) and accelerometers. RLG has a lock-in region in which there is zero output for input angular rates less than 0.1deg/sec. The lock-in region is generated by the imperfect mirrors in RLG. To avoid the lock-in region, sinusoidal motion which is called dither motion is applied on RLG. Therefore without the fault in LINS, the dither motion must be measured by RLG/accelerometer. In this paper, we propose the method to detect the fault of LINS through checking out whether or not the dither motion is always measured by RLG/accelerometer using the Fast Fourier Transformation(FFT) on the real time. The feasibility of the fault detection method proposed in this paper is verified through the stationary and van test.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.10
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• pp.513-519
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• 2001

Home-based Lazy Release Consistency (HLRC) shows poor performance on lock based applications because of two reasons:(1) a whole page is fetched on a page fault while actual modification is much smaller , and(2) the home is at the fixed location while access pattern is migratory, In this paper we present an efficient lock protocol for HLRC. In this protocol, the pages that are expected to be used by acquirer selectively updated using diffs. The diff accumulation problem is minimized by limiting the size of diffs to be sent for each page. Our protocol reduces the number or page faults inside critical sections because pages can be updated by applying locally stored diffs . This reduction yields the reduction of average lock waiting time and the reduction of message amount. The experiment with five applications shows that our protocol archives 2%~40% speedup against base HLRC for four applications.

• The KIPS Transactions:PartB
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• v.19B no.2
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• pp.127-134
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• 2012

Video digital door lock(VDDL) system detects people who access to the door and acquires the human image. Design considerations is that current consumption must be minimized by applying fast human detection algorithm because of battery-based operation. Since the digital door lock takes an image through a fixed camera, detection of a person based on background image leads to high degree of reliability. This paper deals with a single human detection algorithm suitable for VDDL with fulfilling these requirements such that it detects a moving object in an image, then identifies whether the object is a person or not using image processing. The proposed image processing algorithm consists of two steps: Firstly, it detects the human image region using both background image and skin color information. Secondly, it identifies the person using polar histogram based on proportional information of human body. Proposed algorithm is implemented in VDDL and is verified the performance through experiments.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.71-72
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• 2007

대역 제한된 DS/SS 시스템의 상관 함수는 최고 값이 나타나는 시점과 함께 이른 또는 늦은 상관시간 옵셋 영역에서 극소 또는 극대로 나타나는 시점을 특징점으로 갖는다. 이 가운데 이른 상관시간옵셋 영역의 상관 함수는 다중경로 신호에 의해 덜 왜곡되기 때문에 이 영역의 상관 함수를 이용해 부호 동기를 추적하여 유지할 수 있다면 EL-DLL (delay lock loop with early minus late discriminator) 보다 추적편이를 줄일 수 있다. 본 논문에 이런 특성을 이용하는 추적편이 완화 기법을 제안하고, 모의실험을 통해 성능을 알아본다.

• Journal of Practical Engineering Education
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• v.16 no.3_spc
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• pp.327-332
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• 2024

The spread of smart phones provides users with a variety of services, making their lives more convenient. In particular, financial transactions can be easily made online after user authentication using a smart phone. Users easily access the service by authenticating using a PIN, but this makes them vulnerable to social engineering attacks such as spying or recording. We aim to increase security against social engineering attacks by applying the authentication method including imaginary numbers when entering a password at the door lock to smart phones. Door locks perform PIN authentication within the terminal, but in smart phones, PIN authentication is handled by the server, so there is a problem in transmitting PIN information safely. Through the proposed technique, multiple PINs containing imaginary numbers are generated and transmitted as processed values such as hash values, thereby ensuring the stability of transmission and enabling safe user authentication through a technique that allows the PIN to be entered without exposure.

• Journal of the Korea Society of Computer and Information
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• v.26 no.9
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• pp.1-12
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• 2021

In this paper, we propose a tool called ARCAV (Atomatic Recovery of CUDA Atomicity violation) to automatically repair atomicity violations in GPU (Graphics Processing Unit) program. ARCAV monitors information of every barrier and memory to make actual memory writes occur at the end of the barrier region or to make the program execute barrier region again. Existing methods do not repair atomicity violations but only detect the atomicity violations in GPU programs because GPU programs generally do not support lock and sleep instructions which are necessary for repairing the atomicity violations. Proposed ARCAV is designed for GPU execution model. ARCAV detects and repairs four patterns of atomicity violations which represent real-world cases. Moreover, ARCAV is independent of memory hierarchy and thread configuration. Our experiments show that the performance of ARCAV is stable regardless of the number of threads or blocks. The overhead of ARCAV is evaluated using four real-world kernels, and its slowdown is 2.1x, in average, of native execution time.