• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.2
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• pp.179-183
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• 2013

This paper report on experimental results of 5-level inverter by DC divided link voltage. We have alreday reported that DC divided link valtage comes to be able to reduse harmonic of out line voltage. So we tested whether DC divided link voltage can reduce harmonics in experimental setup. This paper shows simulation results and experimental results. And we confirmed that DC divided link voltage can also apply in experimental setup.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.10
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• pp.544-554
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• 1999

Multi-level inverters are now receiving widespread interest form the industrial drives for high power variable speed applications. Especially, for the high power variable speed applications, a diode clamped multi-level inverter has been widely used. However, it has the inherent problem that the voltage of the link capacitors fluctuates. This paper describes a voltage control scheme effectively to suppress the DC-link potential fluctuation for a diode clamped four-level inverter. The current to flow from/into the each link capacitor is analyzed and the operation limit is obtained when a conventional SVPWM is used. To overcome the operation limit, a modified carrier-based SVPWM is proposed. Various simulation and experiment results are presented to verify the proposed voltage control scheme for DC-link voltage balancing.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.370-375
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• 1992

This paper deals with the scheduling and simulation for FMC(Flexible Manufacturing Cells). In order to achieve CIM, there is a critical need to link factory level and machine level. The primary functions performed by this link for all jobs issued to the shop floor and cell include short-term scheduling and dynamic operational scheduling. Here, hierarchical control structure is introduced to define these functions. And Intelligent scheduling through expert module is adopted for efficiency of FMC operation. Computer simulation reveals that expert scheduling method is better than heuristics in various performance index.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.325-329
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• 2000

An effective Carrier-Based PWM scheme that enables the instantaneous quality of each branch point voltage of a diode clamped 4-level inverter to be reduced at a low modulation index is described. This scheme presents a computed zero sequence voltage of PWM by the feedback of both DC-link voltages and load currents. The proposed PWM scheme enables to increase the controllable region of DC-link voltage and makes it possible to operate with small DC-link capacitors. The validity of the proposed PWM scheme is verified by simulation results.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.159-164
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• 1998

This paper proposes a SVPWM (space vector pulse width modulation) strategy for a multi-level voltage source inverter. This strategy is easily implemented as SPWM (sinusoidal pulse width modulation) and has the same DC-link voltage utilization as general SVPWM. The method to keep the voltage balancing of DC-link also is proposed by the analysis model of DC-link voltage fluctuation. The usefulness of the proposed SVPWM is verified through the simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.4
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• pp.291-296
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• 2022

Capacitor is one of the reliability-critical components in power converters. The lifetime of the capacitor decreases as the operating temperature increases, and power losses caused by capacitor current are the main cause of the capacitor temperature increase. Therefore, various studies are being conducted to improve the lifetime of the capacitor by reducing the current of DC-link capacitors. In this study, pulse width modulation methods proposed for improving the lifetime of DC-link capacitors of the three-level NPC inverter are comparatively analyzed. The lifetime evaluation of the DC-link capacitor under different modulation methods is performed at component level first and then system level by considering all capacitors by applying Monte Carlo simulation. Furthermore, their effects on the efficiency and THD of the output current are also considered.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1240-1255
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• 1996

This paper suggests power optimization technique in multi-level SCPC system as a method for efficient utilization of limited satellite power. The power optimization is realized by optimal assignment of satellite input carrier powers considering interference and noise generated in up-link and down-link. The Fletcher-Powell algorithm searching minimum(or maximum) point using gradient information is used to detemine the optimal input carrier powers. To apply Flectcher-Powell algorithm mathematical descriptions and their partial derivatives to interference and nose are presented. Because a target, which should be optimized, is satellite input carrier power, amplitude of each carrier group will be assumed to be an independent variable. The performance criterion for optimal power assignmentis classified into 4 categories with respect to CNR of destination receiver earth station to meet the requirement for various satellite link environment. Simulation results for two-level, four-level and six-level SCPC system are presented.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1261-1264
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• 1996

This paper presents the design of a neural network based PWM technique for a three level inverter of electric trains. A three-level inverter has several advantages compared with a two-level inverter in this application. In viewpoint of correcting unbalance of DC-link voltage, a novel method is developed and verified in computer simulation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.4
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• pp.8-15
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• 2013

This paper proposes a DC-link voltage variation compensation method for a 3-level single phase converter for high-speed trains. Since 3-level NPC(Neutral Point Clamped) type converters have the split DC-link causing the inherent problem of voltage fluctuations in the upper and lower capacitors, reducing the voltage difference between the top and bottom capacitors is required. In this paper, compensation time proportional to the voltage difference is added to PWM switching time to solve the voltage variation. The compensation time is obtained by a PI controller. Simulation results demonstrate the validity of the proposed method.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.5
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• pp.422-428
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• 2013

Recently, we use a static synchronous compensator(STATCOM) with cascaded H-bride topologies, because it is easy to increase capacity and to reduce total harmonic distortion(THD). When we use equipment for reactive power compensation, dc-link voltage unbalances occur from several reasons although loads are balanced. In the past, switching pattern change of single phase inverter and reference voltage magnitude change of inverter equipped with power sensor have been used for dc-link voltage balance. But previous methods are more complicated and expensive because of additional component costs. Therefore, this paper explains reasons of dc-link voltage unbalance and proposes solution. This solution is complex method that is composed of reference voltage magnitude change of inverter without additional hardware and shifted phase angle of inverter reference voltages change. It proves possibility through 1000[KVA] system simulation.