• Journal of Korean Library and Information Science Society
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• v.53 no.2
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• pp.189-214
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• 2022

The purpose of this study is to provide an understanding of the current status of picture book-related research in Korea. For this purpose, 1,660 picture book-related research papers produced in Korea by 2021 were analyzed. The results revealed through the analysis are summarized as follows. First, research papers began to appear in the mid-1990s and began to increase significantly around 2010. Second, the journal with the most research papers was 『Journal of Children's Literature and Education』, accounting for 17.7% of the total. Third, the representative researchers who led the production of the papers are Eun-Ja Hyun and Hea-Sook Jo. Fourth, by research type, individual research papers accounted for 39% and joint research 61%. Fifth, as a result of the analysis of the research topic, the study of the contents (analysis) of picture books (33.4%), the study of the effect of picture books (29.6%), and the study of perception, reaction, and experience of picture books (18.0%) were in order. Sixth, as a result of the research method analysis, experimental studies (35.7%), content analysis (33.7%), literature studies (13.3%), and qualitative studies (9.3%) were in order. Based on the results of the analysis, the researcher suggested diversifying the research production route, expanding the trend of collaboration between universities and the field, diversifying research topics, and enhancing the validity and diversity of research methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2A
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• pp.209-215
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• 2010

This paper describes a design of variable-length FFT/IFFT processor (VL_FCore) for OFDM-based multi-standard communication systems. The VL_FCore adopts in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate various FFT lengths in the range of $N=64{\times}2^k\;(0{\leq}k{\leq}7)$. To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The VL_FCore synthesized with a $0.35-{\mu}m$ CMOS cell library has 23,000 gates and 32 Kbytes memory, and it can operate with 75-MHz@3.3-V clock. The 64-point and 8,192-point FFT's can be computed in $2.25-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of various OFDM-based systems.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.45-53
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) encoding. Previous CAVLC architectures search all of the coefficients to find statistic characteristics in a block. However, it is unnecessary information that zero coefficients following the last position of a non-zero coefficient when CAVLC encodes residual coefficients. In order to reduce this unnecessary operation, we propose two techniques, which detect the first and last position of non-zero coefficients and arrange non-zero coefficients sequentially. By adopting these two techniques, the required processing time was reduced about 23% compared with previous architecture. It was designed in a hardware description language and total logic gate count is 16.3k using 0.18um standard cell library Simulation results show that our design is capable of real-time processing for $1920{\times}1088\;30fps$ videos at 81MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.393-396
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• 2009

This paper describes a design of variable-length FFT/IFFT processor for OFDM-based communication systems. The designed FFT/IFFT processor adopts the in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate FFT lengths of $N=64{\times}2^k$ ($0{\leq}k{\leq}7$). To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The processor synthesized with a $0.35-{\mu}m$ CMOS cell library can operate with 75-MHz@3.3-V clock, and 64-point and 8,192-point FFT's can be computed in $2.55-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of wireless LAN, DMB, and DVB systems.

• Nutrition Research and Practice
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• v.13 no.5
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• pp.399-409
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• 2019

BACKGROUND/OBJECTIVES: This study was designed to provide scientific evidence on the effectiveness of worksite-based dietary intervention to reduce obesity among overweight/obese employees. MATERIALS/METHODS: Electronic search was performed using Ovid Medline, Embase, Cochrane Library, and CINAHL databases. The keywords used were "obesity," "nutrition therapy," and "worksite." The internal validity of the randomized controlled trials (RCTs) was assessed using the Cochrane's Risk of Bias. Meta-analysis of selected studies was performed using Review Manager 5.3. RESULTS: A total of seven RCTs with 2,854 participants were identified. The effectiveness of dietary interventions was analyzed in terms of changes in weight, body mass index (BMI), total cholesterol, and blood pressure. The results showed that weight decreased with weighted mean difference (WMD) of -4.37 (95% confidence interval (CI): -6.54 to -2.20), but the effectiveness was statistically significant only in short-term programs < 6 months (P = 0.001). BMI also decreased with WMD of -1.26 (95% CI: -1.98 to -0.55), but the effectiveness was statistically significant only in short-term programs < 6 months (P = 0.001). Total cholesterol decreased with WMD of -5.57 (95% CI: -9.07 to -2.07) mg/dL, demonstrating significant effectiveness (P = 0.002). Both systolic (WMD: -4.90 mmHg) and diastolic (WMD: -2.88 mmHg) blood pressure decreased, demonstrating effectiveness, but with no statistical significance. CONCLUSIONS: The worksite-based dietary interventions for overweight/obese employees showed modest short-term effects. These interventions can be considered successful because weight loss was below approximately 5-10 kg of the initial body weight, which is the threshold for the management of obesity recommended by the Scottish Intercollegiate Guideline Network (SIGN).

• Clinics in Shoulder and Elbow
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• v.26 no.2
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• pp.182-190
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• 2023

Elbow traumas represent a relatively common condition in clinical practice. However, there is a lack of evidence regarding the most accurate tests for screening these potentially serious conditions and excluding elbow fractures. The purpose of this investigation was to analyze the literature concerning the diagnostic accuracy of clinical tests for the detection or exclusion of suspected elbow fractures. A systematic review was performed using the Preferred Reporting Items for a Systematic Review and Meta-analysis of Diagnostic Test Accuracy Studies (PRISMA-DTA) guidelines. Literature databases including PubMed, Cumulative Index to Nursing and Allied Health Literature, Diagnostic Test Accuracy, Cochrane Library, the Web of Science, and ScienceDirect were searched for diagnostic accuracy studies of subjects with suspected traumatic elbow fracture investigating clinical tests compared to imaging reference tests. The risk of bias in each study was assessed independently by two reviewers using the Quality Assessment of Diagnostic Accuracy Studies 2 checklist. Twelve studies (4,485 patients) were included. Three different types of index tests were extracted. In adults, these tests were very sensitive, with values up to 98.6% (95% confidence interval [CI], 95.0%-99.8%). The specificity was very variable, ranging from 24.0% (95% CI, 19.0%-30.0%) to 69.4% (95% CI, 57.3%-79.5%). The applicability of these tests was very high, while overall studies showed a medium risk of bias. Elbow full range of motion test, elbow extension test, and elbow extension and point tenderness test appear to be useful in the presence of a negative test to exclude fracture in a majority of cases. The specificity of all tests, however, does not allow us to draw useful conclusions because there was a great variability of results obtained.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1E
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• pp.14-19
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• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.361-364
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• 2002

Shortest path problem belongs to the combinatorial optimization problem and plays an important role in the field of computer aided design. It can either be directly applied as in the case of routing or serves as a important subroutine in more complex problems. In this paper, a systolic array for the SSSP(single-source shortest path problem) was derived. The array was modeled and simulated in RTL level using VHDL, then synthesized to a schematic and finally implemented to a layout using the cell library based on 0.35 $\mu\textrm{m}$ CMOS 1-poly 4-metal CMOS technology.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.226-229
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• 2000

In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.