• Proceedings of the KAIS Fall Conference
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• 2010.05a
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• pp.18-23
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• 2010

4$\times$4 Butler Matrix structure has been presented in this paper. It can passes the signal with equal power level and phase difference in the 824MHz to 894MHz frequency of the cellular band. Conventional Butler Matrix was implemented as a single layer substrate structure, but in this paper, we use multi-layer substrate structure and eventually we could get it reduced in size than others. We also used the LTCC coupler to reduce the size effectively, instead of using $90^{\circ}$ hybrid coupler composed of microstrip structure. we used Designer V3.5 Ansoft HFSS V11 for design of 4$\times$4 Butler matrix. Finally, we get good agreements between simulation and experimental results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.7 s.110
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• pp.694-705
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• 2006

In this paper, the linear active phased array antenna system operated in Ku DBS band was designed and experimented. The antenna system was composed of sixteen radiating active channels and Wilkinson power combiners with 16-channel inputs, a stabilizing DC bias and phase control board. Electrical beams of the antenna system can be formed by controling the phase-states of 3-bit digital phase shifter inside each active channel by virtue of the phase control board. The amplitude and phase deviations measured between active channels were less than ${\pm}0.8dB$ and ${\pm}15^{\circ}$, respectively, and the noise figure of each active channel was measured less than 1.2 dB in the operating band. The measured performances of the overall antenna system showed the antenna gain of more than 23.07 dBi and the sidelobe level of less than -11.17 dBc, and the bore-sight cross-polarization level of less than -12.75 dBc in the operating band. Also, by phase-controlling active channels, the beam scan patterns at $10^{\circ},\;20^{\circ},\;30^{\circ}$ were measured, and the losses caused by the corresponding beam scanning were 1.1 dB, 2.5 dB and 3.6 dB from the measurements, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.4
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• pp.413-420
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• 2003

In this paper, the correction method of antenna beam direction errors is introduced which caused by frequency scan effect in active Phased may antenna for satellite communications. The antenna makes the beam directional error from frequency scan effect when it has dual beam may structure with asymmetrical series connection, their frequencies are different and for from each other, their 3dB beamwidth is narrow, and scan range is wide. By proposed equations, estimated beam direction error angles can be calculated and active phase shifter control values also can be calculated to compensate them. In this paper, the active phased array antenna system was fabricated to measure beam direction errors both before and after correction, which has dual beam from 32${\times}$4 main level array and 4${\times}$2 second level array, frequency deviation 500 MHz max.(6.7 %) at 7.25 GHz∼7.75 GHz ranges, 0$^{\circ}$∼${\pm}$35$^{\circ}$nm ranges, and 35.6 dBi gain with 2.2$^{\circ}$3 dB beam width. Its beam direction error by frequency san effect which was 2.5$^{\circ}$max., was reduced to 0.2$^{\circ}$max. after correction. This was 7 dB improvement of signal loss. The active phased array antenna can accurately track the target satellite for communications by this proposed correction method.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

• Journal of radiological science and technology
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• v.32 no.4
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• pp.361-370
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• 2009

The image quality management of bone mineral density is the responsibility and duty of radiologists who carry out examinations. However, inaccurate conclusions due to lack of understanding and ignorance regarding the methodology of image quality management can be a fatal error to the patient. Therefore, objective of this paper is to understand proper image quality management and enumerate methods for examiners and patients, thereby ensuring the reliability of bone mineral density exams. The accuracy and precision of bone mineral density measurements must be at the highest level so that actual biological changes can be detected with even slight changes in bone mineral density. Accuracy and precision should be continuously preserved for image quality of machines. Those factors will contribute to ensure the reliability in bone mineral density exams. Proper equipment management or control methods are set with correcting equipment each morning and after image quality management, a phantom, recommended from the manufacturer, is used for ten to twenty-five measurements in search of a mean value with a permissible range of ${\pm}1.5%$ set as standard. There needs to be daily measurement inspections on the phantom or at least inspections three times a week in order to confirm the existence or nonexistence of changes in values in actual bone mineral density. in addition, bone mineral density measurements were evaluated and recorded following the rules of Shewhart control chart. This type of management has to be conducted for the installation and movement of equipment. For the management methods of inspectors, evaluation of the measurement precision was conducted by testing the reproducibility of the exact same figures without any real biological changes occurring during reinspection. Bone mineral density inspection was applied as the measurement method for patients either taking two measurements thirty times or three measurements fifteen times. An important point when taking measurements was after a measurement whether it was the second or third examination, it was required to descend from the table and then reascend. With a 95% confidence level, the precision error produced from the measurement bone mineral figures came to 2.77 times the minimum of the biological bone mineral density change. The value produced can be stated as the least significant change (LSC) and in the case the value is greater, it can be stated as a section of genuine biological change. From the initial inspection to equipment moving and shifter, management must be carried out and continued in order to achieve the effects. The enforcement of proper quality control of radiologists performing bone mineral density inspections which brings about the durability extensions of equipment and accurate results of calculations will help the assurance of reliable inspections.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).