• Journal of the Korea Concrete Institute
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• v.20 no.4
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• pp.415-421
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• 2008

Reinforced concrete starts to corrode when the chloride ion concentration which is the sum of included in concrete and penetrated from environments exceeds a certain level of critical chloride concentration. Therefore each country regulates the upper bounds of chloride amount in concrete and the regulations are different for each country due to its circumstances. In this study, the critical threshold chloride content according to unit cement amount is empirically calculated to propose a reasonable regulation method on the chloride amount. As a result, the critical threshold chloride content increases considerably according to cement content and it agrees with the established theories. The present regulations on total chloride amount 0.3 or 0.6 kg chloride ions per $1\;m^3$ of concrete does not reflect the influences of mix design, environmental conditions and etc. So it can be said that it is more reasonable to regulate the critical threshold chloride content by the ratio of chloride amount per unit cement content than by the total chloride content in $1\;m^3$ of concrete.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1107-1114
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• 2004

System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.

• Journal of Navigation and Port Research
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• v.36 no.5
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• pp.329-338
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• 2012

The Institute Time Clauses-Hulls 1/10/83 has been using widely with attachment and/or endorsement of the Institute Warranties 1/7/76 stipulating vessel's trading limits. Taking into consideration of several changes and renewals on the contents of the Institute Time Clauses-Hulls for clarifying the clauses themselves with development on technology of vessel's construction and navigational equipments up to the present, the clauses on the Institute Warranties 1/7/76 should have been changed and/or renewed. Moreover, the insured still has been burdening additional premium in vessel's navigating and / or calling to the areas stipulated in the Institute Warranties 1/7/76 regardless of any changes of marine business environments. Thus, this study aims to analyze the Institute Warranties 1/7/76 as well as to suggest a reasonable level of additional premium for breach of Institute warranties through not only a comparative analysis between the Institute Warranties clauses and those of the corresponding Institute Warranties using in the Japanese Fire and Marine Insurance companies but also consideration of current circumstances on changes in climatic conditions, vessel design, navigation and communication requirements and capabilities.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.329-331
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• 2018

In this paper, we propose a monitoring system that starts with the supply of raw materials for threading, is processed into a lathe machine, and checks for defects of the product are automatically performed by the robot with Smart Factory technology through assembly and disassembly. Completion check according to the production instruction quantity and production instruction is made by checking the production status according to whether or not the raw material is worn by the displacement sensor, and checking the pitch and the contour of the processed female and male to determine OK and NG. The robotic system acts as a relay for loading and unloading of raw materials, pallet transfer, and overall process, and it acts as an intermediary for organically driving. The location information of the threaded products is collected by using the non-contact wireless tag and the energy saving system Production efficiency and utilization rate were checked. The environmental sensor collects the air-conditioning environment data (temperature, humidity), measures the temperature and humidity accurately, and checks the quality of product processing. It monitors and monitors the driving hazard level environment (overheating, humidity) of the product. Controls for CNC and robot module PLC as a heterogeneous system.

• The Transactions of the Korea Information Processing Society
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• v.1 no.1
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• pp.114-128
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• 1994

It is very difficult for a nonprofessional programmer in Koera to write a program with very High Level Language such as, V,REFINE, GIST, and SETL, because the semantic primitives of these languages are based on predicate calculus, set, mapping, or testricted natural language. And it takes time to be familiar with these language. In this paper, we suggest a method to reduce such difficulties by programming with the declarative, procedural constructs, and aggregate constructs. And we design and implement an experimental knowledge-based automatic programming system. called HAPS(Hangul Automatic Program System). HAPS, whose input is specification such as Hangul abstract algorithm and datatype or Hangul procedural constructs, and whose output is C program. The method of operation is based on rule-based and program transformation technique, and the problem transformation technique. The problem area is general problem. The control structure of HAPS accepts the program specification, transforms this specification according to the proper rule in the rule-base, and stores the transformed program specification on the global data base. HAPS repeats these procedures until the target C program is fully constructed.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• Korean Chemical Engineering Research
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• v.55 no.2
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• pp.270-274
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• 2017

Formic acid has been known as one of key sources of hydrogen. Among various monometallic catalysts, hydrogen can be efficiently produced on Pd catalyst. However, the catalytic activity of Pd is gradually reduced by the blocking of active sites by CO, which is formed from the unwanted indirect oxidation of formic acid. One of promising solutions to overcome such issue is the design of alloy catalyst by adding other metal into Pd since alloying effect (such as ligand and strain effect) can increase the chance to mitigate CO poisoning issue. In this study, we have investigated formic acid deposition on the bimetallic $Pd/Pd_3Fe$ core-shell nanocatalyst using DFT (density functional theory) calculation. In comparison to Pd catalyst, the activation energy of formic acid dehydrogenation is greatly reduced on $Pd/Pd_3Fe$ catalyst. In order to understand the importance of alloying effects in catalysis, we decoupled the strain effect from ligand effect. We found that both strain effect and ligand effect reduced the binding energy of HCOO by 0.03 eV and 0.29 eV, respectively, compared to the pure Pd case. Our DFT analysis of electronic structure suggested that such decrease of HCOO binding energy is related to the dramatic reduction of density of state near the fermi level.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.634-639
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• 2006

In this paper an MMIC 2-stage power amplifier is designed and fabricated for 5GHz wireless LAN applications using $0.5{\mu}m$ gate length PHEMT transistors. The PHEMT gate width is optimized in order to meet the linearity and efficiency of the MMIC power amplifier. The $0.5{\mu}m\times600{\mu}m$ PHEMT for the drive stage and $0.5{\mu}m\times3000{\mu}m$ PHEMT for the amplification stage are the optimized sizes to achieve more than 25dBc of third order IMD at the power level of 3dB back-off from the input P1dB and more than 22dBm output power under a supply voltage of 3.3V. The two-stage MMIC power amplifier is designed to be used for the both of HIPERLAN/2 and IEEE 802.11a because of its broadband characteristics. The fabricated PHEMT MMIC power amplifier exhibits a 20.1dB linear power gain, a maximum 22dBm output power, a 24% power added efficiency under 3.3V supply voltage. The input and output on-chip matching circuits are included on a chip of $1400\times1200{\mu}m^2$.

• KSBB Journal
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• v.28 no.1
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• pp.60-64
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• 2013

Two strains were isolated from the traditional Deep Blue Sediment Dye of Polygoum tinctoria, Niram, and temporarily named Niram A and Niram B, respectively. The phylogenetic analysis revealed that strain Niram A and B were closely related to the members of the genus Comamonas and Microbacterium, respectively. Strain Niram A exhibited the highest 16S rRNA gene sequence similarity to C. aquatica LMG $2370^T$ (98.06%). Strain Niram B showed 100% homology with M. oxydans DSM 20578T and M. maritypicum DSM $12512^T$. The growth of the strain Niram A and B was not inhibited in Niram medium containing high calcium concentration without free sugar as carbon source. The reducing Niram is greenish. Therefore, the reducing ability on the Niram of the strains Niram A and B were determined with the color difference of the $a^*$ values of Niram fermented-fluids. The $a^*$ value indicates the level of redness (positive value) or greenness (negative value). The green color is increasing towards the negative value. In all samples fermented for 10 days, the $a^*$ values among samples were no significant difference. However, samples fermented for 15 days have an appreciable change. After fermentation for 15 days, the control Niram sample had $-3.96{\pm}0.02$ of the $a^*$ value. On the other hand, the Niram samples fermented with the strain Niram A and B showed $-4.20{\pm}0.02$ of the $a^*$ value and $-7.86{\pm}0.03$ of the $a^*$ value, respectively. In the reducing ability on the Niram, the strain Niram B was significantly better than the strain Niram A.