• Transactions on Electrical and Electronic Materials
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• v.2 no.3
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• pp.28-32
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• 2001

It was studied in the present work how the thermal cycling performance of LOC (lead on chip) packages depends on the package construct or leadframe materials. First, package body thickness and Au wire diameter were manipulated for the selection of proper package design. Secondly, two different types of leadframe materials (i.e. copper and 52%Fe-48%Ni alloy) were tested to determine the better material for improved reliability margin of plastically encapsulated microelectronic packages. This work shows that manipulating package body thickness was more effective than an increase of Au wire from 23$\mu\textrm{m}$ to 33$\mu\textrm{m}$ for the prevention of wire debonding failure. Further, this work indicates that the LOC packages including the copper leadframes can be more susceptible to thermal cycling reliability degradation due to chip cracking than those including the alloy leadframes.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package) is the IC package using lead frame, which is the type of low cost package for white electronics, auto mobile, desktop PC, and so on. Its performance is not excellent compared to BGA or flip-chip CSP, but it has been used mostly because of low price of TSOP package. However, it has been issued in TSOP package that thermal deflection of lead frame occurs frequently during molding process and Au wire between semiconductor die and pad is debonded. It has been required to solve this problem through substituting materials with low CTE and improving structure of lead frame. We focused on developing the lead frame structure having thermal stability, which was carried out by numerical analysis in this study. Thermal deflection of lead frame in TSOP package was simulated with positions of anti-deflection adhesives, which was ranging 198 um~366 um from semiconductor die. It was definitely understood that thermal deflection of TSOP package with anti-deflection adhesives was improved as 30.738 um in the case of inside(198 um), which was compared to that of the conventional TSOP package. This result is caused by that the anti-deflection adhesives is contributed to restrict thermal expansion of lead frame. Therefore, it is expected that the anti-deflection adhesives can be applied to lead frame packages and enhance their thermal deflection without any change of substitutive materials with low CTE.

• Journal of the Korean Society for Nondestructive Testing
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• v.12 no.4
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• pp.18-25
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• 1993

This paper is to aim the microdefect evaluation of If package into a quantitative from NDI's image processing of ultrasonic wave. (1) Automatically repeated discrimination analysis method can be devided in the category of all kind of defects on IC package, and also can be possible to have a sampling of partial delamination. (2) It is possible that the information of edge section in silicon chip surrounding can be extractor by the partial image processing of IC package. Also, the crack detection is possible between the resin part and lead frame.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.53-58
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• 2013

An innovative packaging solution, Flip Chip with Copper (Cu) Column bond on lead (BOL) Enhanced Process (fcCuBE$^{(R)}$) delivers a cost effective, high performance packaging solution over typical bond on capture pad (BOC) technology. These advantages include improved routing efficiency on the substrate top layer thus allowing conversion functionality; furthermore, package cost is lowered by means of reduced substrate layer count and removal of solder on pad (SOP). On the other hand, as electronic packaging technology develops to meet the miniaturization trend from consumer demand, reliability testing will become an important issue in advanced technology area. In particular, electromigration (EM) of flip chip bumps is an increasing reliability concern in the manufacturing of integrated circuit (IC) components and electronic systems. This paper presents the results on EM characteristics on BOL and BOC structures under electrical current stressing in order to investigate the comparison between two different typed structures. EM data was collected for over 7000 hours under accelerated conditions (temperatures: $125^{\circ}C$, $135^{\circ}C$, and $150^{\circ}C$ and stress current: 300 mA, 400 mA, and 500 mA). All samples have been tested without any failures, however, we attempted to find morphologies induced by EM effects through cross-sectional analysis and investigated the interfacial reaction characteristics between BOL and BOC structures under current stressing. EM damage was observed at the solder joint of BOC structure but the BOL structure did not show any damage from the effects of EM. The EM data indicates that the fcCuBE$^{(R)}$ BOL Cu column bump provides a significantly better EM reliability.

• Journal of Welding and Joining
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• v.17 no.1
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• pp.124-132
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• 1999

Thermal fatigue strength of the solder joints is the most critical issue for TSOP(Thin Small Outline Package) because the leads of this package are extremely short and thermal deformation cannot be absorbed by the deflection of the lead. And the TSOP body can be subject to early fatigue failures in thermal cycle environments. This paper was discussed distribution of thermal stresses at near the joint between silicon chip and die pad and investigated their reliability of solder joints of TSOP with 42 alloy clad lead frame on printed circuit board through FEM and 3 different thermal cycling tests. It has been found that the stress concentration around the encapsulated edge structure for internal crack between the silicon chip and Cu alloy die pad. And using 42 alloy clad, The reliability of TSOP body was improved. In case of using 42 alloy clad die pad(t=0.03mm). $$\sigma$_{VMmax}$ is 69Mpa. It is showed that 15% improvement of the strength in the TSOP body in comparison with using Cu alloy die pad $($\sigma$_{VMmax}$=81MPa). In solder joint of TSOP, the maximum equivalent plastic strain and Von Mises stress concentrate on the heel of solder fillet and crack was initiated in it's region and propagated through the interface between lead and solder. Finally, the modified Manson-Coffin equation and relationship of the ratio of $N_{f}$ to nest(η) and cumulative fracture probability(f) with respect to the deviations of the 50% fracture probability life $(N_{f 50%})$ were achieved.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.19-24
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• 2000

To make stacked chip packages far high-density packaging of memory chips used in workstations or PC severs, several lead-frames are to be connected vertically. Fer this purpose. Sn or Sn/Ag were electrochemically deposited on Cu lead-frames and their microstructures were examined by XRD and SEM. Then, two specimens were annealed at $250^{\circ}C$ for 10 min. and pressed to be joined. The shear stresses of joined lead-frames were measured fur comparison. In the case of Sn only, $Cu_3Sn$ was formed by the reaction of Sn and Cu lead-frames. In the case of Sn/Ag, besides $Cu_3Sn$. $Ag_3Sn$ was formed by the reaction of Sn and Ag. Compared to joined specimens made from Sn only, those made from Sn/Ag showed 1.2 times higher shear stress. This was attributed to the $Ag_3Sn$ phase formed at the joined interface.

• Proceedings of the KWS Conference
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• 2002.05a
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• pp.269-271
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• 2002

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.3
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• pp.265-271
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• 2008

TCP(Tape Carrier Package), COG (Chip On Glass), COF(Chip On Film) are three methods for connecting LDI(LCD Driver IC) with LCD panels. Especially COF is growing its portion of market place because of low cost and fine pitch correspondence. But COF has a problem of the lead broken failure in LCD module process and the usage of customer. During PCB (Printed Circuit Board) bonding process, the mismatch of the coefficient of thermal expansion between PCB and D-IC makes stress-concentration in COF lead, and also D-IC bending process during module assembly process makes the level of stress in COF lead higher. As an affecting factors of lead-broken failure, the effects of SR(Solder Resister) coating on the COF lead, surface roughness and grain size of COF lead, PI(Polyimide) film thickness, lead width and the ACF(Anisotropic Conductive Film) overlap were studied, The optimization of these affecting manufacturing processes and materials were suggested and verified to prevent the lead-broken failure.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.69-73
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• 2008

This article shows that the susceptibility of the device pattern to thermal stress-induced damage has a strong dependence on its proximity to the device comer in semiconductor devices utilizing lead-on-chip (LOC) die attach technique. The result, as explained based on numerical calculation and experiment, indicateds that the stress-driven damage potential of the passivation layer is the highest at the device comer. Thus, the bonding pads, which are very susceptible to passivation damage, should be designed to be located along the central region rather than the peripheral region of the device.

• Journal of the Korean Society of Industry Convergence
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• v.12 no.4
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• pp.215-219
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• 2009

A packaging technology based on flip-chip bonding and Pb-free solder for silicon pressure sensors on printed circuit board (PCB) is presented. First, the bump formation process was conducted by Pb-free solder. Ag-Sn-Cu solder and the pressed-screen printing method were used to fabricate solder bumps. The fabricated solder bumps had $189-223{\mu}m$ width, $120-160{\mu}m$ thickness, and 5.4-6.9 standard deviation. Also, shear tests was conducted to measure the bump shear strength by a Dage 2400 PC shear tester; the average shear strength was 74 g at 0.125 mm/s of test speed and $5{\mu}m$ shear height. Then, silicon pressure sensor packaging was implemented using the Pb-free solder and bump formation process. The characteristics of the pressure sensor were analogous to the results obtained when the pressure sensor dice are assembled and packaged using the standard wire-bonding technique.