• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2001년도 춘계학술대회 논문집
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• pp.77-80
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• 2001

IC lead frame needs the precision shape for good efficiency. In the blanking process, there are many parameter effected the dimensional accuracy : lead width, blanking order, striper force, tool clearance etc. In this research, the4 undesirable defects appeared in the final blanking process. so we measured the deflection of lead according to the stripper force using $PAM-STAMP_{TM}$. In the result, the deflection was decreased by increasing the stripper force properly. and we changed the blanking order on the test model. In the blanking order, deflection is good from the outer line position blanking to center line position. so we can design the precision die without tryout by the prediction of the lead deflection.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.63-85
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• 1999

$\cdot$New CSP using Lead Frame and solder ball techniques. $\cdot$EMC needs high filler content, low CTE and high flexural modulus. $\cdot$Solder Joint Reliability improved by anchor leads. .Uniform inner lead shape would be better at capacitance values. $\cdot$Low Assembly cost CSP.

• Journal of Welding and Joining
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• 제13권2호
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• pp.82-95
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• 1995

This paper discusses distribution of thermal stress, strain at near the joint and investigates the reliability of solder joints of electronic devices on a printed circuit board. As Electronic devices are composed of different materials, thermal stresses generate at near the interface, such as solder joints and interface between lC device and lead frame pad due to the differences of thermal expansion coefficients, As results of thermal stress, strain, micro crack often occurs thermal fatigue fracture at the interface of different materials, The initiation and propagation of micro crack depend on the environmental conditions, such as storage temperature and thermal cycling. Finally, this paper experimentally shows a way to suppress micro cracks by using Fe-Ni alloy clad lead frame, and investigates crack and thermal fatigue fracture of TSOP(Thin small outline package) type on printed circuit board.

• 반도체디스플레이기술학회지
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• 제10권3호
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• pp.61-65
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• 2011

The capabilities of finite elements codes allow now accurate simulations of blanking processes when appropriate materials modelling are used. Over the last decade, numerous numerical studies have focused on the influence of process parameters such as punch-die clearance, tools geometry and friction on blanking force and blank profile. In this study, three dimensional finite element analysis is carried out to design a lead frame blanking die using LS-Dyna3D package. After design of the blanking die, an experiment is also carried out to investigate the characteristics of blanking for nickel alloy Alloy42, a kind of IC lead frame material. In this paper, it has been researched the investigation to examine the influence of process parameters such as clearance and air cylinder pressure on the accuracy of sheared plane. Through the experiment results, it is shown that the quality of sheared plane is less affected by clearance and air cylinder pressure.

• 한국컴퓨터산업학회논문지
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• 제3권9호
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• pp.1177-1188
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• 2002

본 논문에서는 생산현장에서 생산하는 Lead Pin을 생산근로자의 시각으로 품질을 검사하는 방법을 개선하기 위하여, 영상처리 알고리즘을 사용하여 자동으로 품질의 정ㆍ오판별을 검사하기 위한 실시간 영상처리방법을 제안한다. 먼저 영상정보의 실시간 취득을 위하여 C.C.D와 영상취득기(Image frame grabber : DT3153)를 사용하여 초당 30프레임(30 Frame/second)으로 영상을 취득할 수 있는 실시간 영상취득시스템을 구성하였으며, 이를 사용하여 Lead Pin의 영상을 취득하여 Lead pin의 형상을 나타내는 형상프로파일의 영상처리 알고리즘을 사용하여 연구를 수행하였다. Lead Pin의 정품과 비정품을 평가하기 위해 숙련된 작업자에 의해 판별된 정품 100개, 비정품 100개, 전체 200개의 인식대상 물체를 판별한 수행결과 정품을 정품으로 인식하여 판별한 경우는 97%, 비정품을 비정품으로 판별한 경우는 95%로 전체 인식률은 96%의 인식결과를 나타내었으며, 전체 오분류률은 4%를 나타냄을 알 수 있었다.

• 한국정밀공학회지
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• 제22권2호
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• pp.133-138
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• 2005

The deformation of sheet metal due to the residual stress during blanking or piercing process, is numerically simulated by means of a commercial finite element code. Two dimensional plain strain problem is solved and then its result is applied to the deformation analysis of the lead frame. The plain strain element is applied to the 2D problem to observe the Von Mises equivalent stress concentration at the both shearing edges. As the punch penetrates into the sheet material, the stress concentration generated on both edges is getting increased to be the shearing surface. The limits of the punching depth applied to the simulation is 16% and 24% of the sheet thickness for the plain strain element and the hexahedral element, respectively. The hexahedral element and the limit of punching depth were applied to the deformation analysis of the lead frame for the blanking process. The FEM results for the lead deformation were very good agreement with the experimental ones. This paper shows that the coarse mesh has enabled to analyze the lead deformation generated due to the blanking mechanism. This simple approach to save the calculation time will be very effective to the design of the blanking tools in industries.

• International Journal of Precision Engineering and Manufacturing
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• 제2권2호
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• pp.38-47
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• 2001

This paper decribes the development of computer-aided design of a very precise progressice die for lead frame of semiconductor chip. The approach to the system is based on knowledgr-based rules. Knowledge of fie이 experts. This system has been written in AutoLISP using AutoCAD ona personal computer and the I-DEAS drafting programming Language on the I-DEAS mater series drafting with on HP9000/715(64) workstation. Data exchange between AutoCAD and I-DEAS master series drafting is accomplished using DXF(drawing exchange format) and IGES(initial graphics exchange specification) files. This system is composed of six main modules, which are input and shape treatment, production feasibility check, strip layout, data conversion, die layout, and post processing modules. Based on Knowledge-based rules, the system considers several factors, such as V-notches, dimple, pad chamfer, spank, cavity punch, camber, coined area, cross bow, material and thickness of product, complexities of blank geometry and punch profiles, specifications of available presses, and the availability of standard parts. As forming processes and the die design system using 2D geometry recognition are integrated with the technology of process planning, die design, and CAE analysis, the standardization of die part for lead frames requiting a high precision process is possible. The die layout drawing generated by the die layout module s displayed in graphic form. The developed system makes it possible to design and manufacture lead frame of a semiconductor more efficiently.

• 접착 및 계면
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• 제23권4호
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• pp.108-115
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• 2022

본 연구에서는 표면처리된 Cu 리드프레임과 에폭시 컴포지트의 접착강도를 향상시키기 위하여 신규 고분자 접착증진제인 poly(itaconic acid-co-acrylamide) (IAcAAM)를 합성하였다. 이타콘산과 아크릴아마이드를 포함하는 IAcAAM은 라디칼 수성 중합을 통해 제조되었다. IAcAAM의 구조 및 물성은 FT-IR, ¹H-NMR, GPC 및 DSC로 분석하였다. Cu 리드프레임의 표면은 고온, 알칼리, UV 오존으로 처리하였다. 표면처리 후 Cu 리드프레임의 접촉각이 감소함에 따라 Cu 리드프레임/에폭시 컴포지트의 접착강도는 증가하였다. 에폭시 혼합물에 IAcAAM을 첨가함에 따라 Cu 리드프레임/에폭시 컴포지트의 접착강도가 증가하였다. 또한, 에폭시 혼합물에 실리카 함량이 증가할수록 Cu 리드 프레임과 에폭시 컴포지트의 접착강도는 약간 감소하는 경향을 나타내었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• 마이크로전자및패키징학회지
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• 제20권3호
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package)는 가전제품, 자동차, 모바일, 데스크톱 PC등을 위한 저렴한 비용의 패키지로, 리드 프레임을 사용하는 IC패키지이다. TSOP는 BGA와 flip-chip CSP에 비해 우수한 성능은 아니지만, 저렴한 가격 때문에 많은 분야에 널리 사용되고 있습니다. 그러나, TSOP 패키지에서 몰딩공정 할 때 리드프레임의 열적 처짐 현상이 빈번하게 일어나고, 반도체 다이와 패드 사이의 Au 와이어 떨어짐 현상이 이슈가 되고 있다. 이러한 문제점을 해결하기 위해서는 리드프레임의 구조를 개선하고 낮은 CTE를 갖는 재료로 대체해야 한다. 본 연구에서는 열적 안정성을 갖도록 리드프레임 구조 개선을 위해 수치해석적 방법으로 진행하였다. TSOP 패키지에서 리드프레임의 열적 처짐은 반도체와 다이 사이의 거리(198 um~366 um)에서 안티-디플렉션의 위치에 따라 시뮬레이션을 진행하였다. 안티-디플렉션으로 TSOP 패키지의 열적 처짐은 확실히 개선되는 것을 확인 했다. 안티-디플렉션의 위치가 inside(198 um)일 때 30.738 um 처짐을 보였다. 이러한 결과는 리드프레임의 열적 팽창을 제한하는데 안티-디플렉션이 기여하고 있기 때문이다. 그러므로 리드프레임 패키지에 안티-디플렉션을 적용하게 되면 낮은 CTE를 갖는 재료로 대체하지 않아도 열적 처짐을 향상시킬 수 있음을 기대할 수 있다.