• Bulletin of the Korean Mathematical Society
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• v.56 no.1
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• pp.111-130
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• 2019

The concepts of pseudocodeword and pseudoweight play a fundamental role in the finite-length analysis of LDPC codes. The pseudoredundancy of a binary linear code is defined as the minimum number of rows in a parity-check matrix such that the corresponding minimum pseudoweight equals its minimum Hamming distance. By using the value assignment of Chen and Kløve we present new results on the pseudocodeword redundancy of binary linear codes. In particular, we give several upper bounds on the pseudoredundancies of certain codes with repeated and added coordinates and of certain shortened subcodes. We also investigate several kinds of k-dimensional binary codes and compute their exact pseudocodeword redundancy.

• Journal of the Korea Convergence Society
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• v.11 no.6
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• pp.43-49
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• 2020

In spite of the notable advancements of millimeter wave communication technologies, the 60 GHz Wi-Fi is still not widespread yet, mainly due to the high limitation of coverage. Conventionally, it has been hardly possible to support a high data rate with fast beam adaptation while keeping atmospheric beamforming coverage. To solve these challenges in the 60 GHz communication system, holistic system designs are considered. we implemented an enhanced design LDPC decoder enabling 6.72 Gbps coded-throughput with minimal implementation loss, and our proposed phase-tracking algorithm guarantees 3.2 dB performance gain at 1 % PER in the case of 16 QAM modulation and LDPC code-rate 3/4.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5C
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• pp.423-431
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• 2010

In this paper, a modified sum-product algorithm to correct bit errors captured within the trapping sets, which are produced in decoding of low-density parity-check (LDPC) codes, is proposed. Unlike the original sum-product algorithm, the proposed decoding method consists of two stages. Whether the main cause of decoding failure is the trapping sets or not is determined at the first stage. And the bit errors within the trapping sets are corrected at the second stage. In the modified algorithm, the set of failed check nodes and the transition patterns of hard-decision bits are exploited to search variable nodes in the trapping sets. After inverting information of the variable nodes, the sum-product algorithm is carried out to correct the bit errors. As a result of simulation, the proposed algorithm shows continuously improved error performance with increase in the signal-to-noise ratio. It is, therefore, considered that the modified sum-product algorithm significantly reduces or possibly eliminates the error floor in LDPC codes.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.1026-1035
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• 2011

This paper presents generalization and application for the conventional SISO decoding algorithm of Block Turbo Codes. R. M. Pyndiah suggested an iterative SISO decoding algorithm for Product Codes, two-dimensionally combined linear block codes, on AWGN channel. It wascalled Block Turbo Codes. Based on decision of Chase algorithm which is SIHO decoding method, SISO decoder for BTC computes soft decision information and transfers the information to next decoder for iterative decoding. Block Turbo Codes show Shannon limit approaching performance with a little iteration at high code rate on AWGN channel. In this paper we generalize the conventional decoding algorithm of Block Turbo Codes, under BPSK modulation and AWGN channel transmission assumption, to the LLR value based algorithm and suggest an application example such as concatenated structure of LDPC codes and Block Turbo Codes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.216-225
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• 2007

This paper presents bit splitting methods to apply multilevel modulation to iterative codes such as turbo code, low density parity check code and turbo product code. Log-likelihood ratio method splits multilevel symbols to bits using the received in-phase and quadrature component based on Gaussian approximation. However it is too complicate to calculate and implement hardware due to exponential and log calculation. therefore this paper presents Euclidean, MAX and Sector method to reduce the high complexity of LLR method. We propose optimal bit splitting method for three iterative codes.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.835-842
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• 2009

DVB-SSP is a new broadcasting system for hybrid satellite communications, which supports mobile handheld systems and fixed terrestrial systems. However, a critical factor must be considered in upper layer decoding which including erasure Reed-Solomon error correction combined with cyclic redundancy check. If there is only one bit error in an IP packet, the entire IP packet is considered as unreliable bytes, even if it contains correct bytes. IF, for example, there is one real byte error, in an If packet of 512 bytes, 511 correct bytes are erased from the frame. Therefore, this paper proposed two kinds of upper layer decoding methods; LLR-based decoding and hybrid decoding. By means of simulation we show that the performance of the proposed decoding algorithm is superior to that of the conventional one.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.9
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• pp.3458-3481
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• 2021

Existing methods for blind identification of linear block codes without a candidate set are mainly built on the Gauss elimination process. However, the fault tolerance will fall short when the intercepted bit error rate (BER) is too high. To address this issue, we apply the reverse algebra approach and propose a novel "two-step-screening" algorithm by solving the linear error equations on the binary Galois field, or GF(2). In the first step, a recursive matrix partition is implemented to solve the system linear error equations where the coefficient matrix is constructed by the full codewords which come from the intercepted noisy bitstream. This process is repeated to derive all those possible parity-checks. In the second step, a check matrix constructed by the intercepted codewords is applied to find the correct parity-checks out of all possible parity-checks solutions. This novel "two-step-screening" algorithm can be used in different codes like Hamming codes, BCH codes, LDPC codes, and quasi-cyclic LDPC codes. The simulation results have shown that it can highly improve the fault tolerance ability compared to the existing Gauss elimination process-based algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.139-147
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• 2010

A novel turbo coded modulation scheme, called turbo-APPM, for deep space optical communications is constructed. The constructed turbo-APPM is a serial concatenations of turbo codes, an accumulator and a pulse position modulation (PPM), where turbo codes act as an outer code while the accumulator and the PPM act together as an inner code. The generator polynomial and the puncturing rule for generating turbo codes are chosen to show the low bit error rate. At the receiver, the joint decoding is performed by exchanging soft information iteratively between the inner decoder and the outer decoder. In the outer decoder, a local iterative decoding for turbo codes is conducted before transferring soft information to the inner decoder. Poisson distribution is used to model the deep space optical channel. It is shown by simulations that the constructed turbo-APPM provides coding gains over all previously proposed schemes such as LDPC-APPM, RS-PPM and SCPPM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9C
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• pp.848-854
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• 2009

DVB-SSP is a new broadcasting system for hybrid satellite communications, which supports mobile handhold systems and fixed terrestrial systems. An upper layer, including erasure Reed-Solomon error correction combined with cyclic redundancy check. However, a critical factor must be considered in upper layer decoding. If there is only one bit error in an IP packet, the entire IP packet is considered as unreliable bytes, even if it contains correct bytes. If, for example, there is one real byte error, in an If packet of 512 bytes, 511 correct bytes are erased from the frame. Therefore, this paper proposed upper layer decoding methods; hybrid decoding. By means of simulation we show that the performance of the proposed decoding algorithm is superior to that of the conventional one in AWGN channel and TI channel.

• ETRI Journal
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• v.31 no.5
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• pp.585-592
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• 2009

This paper presents a method for decoding high minimal distance ($d_{min}$) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher$d_{min}$ than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high $d_{min}$, several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof-of-concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25-${\mu}m$ CMOS. It outperforms an equivalent LDPC-like decoder by 1 dB at BER=$10^{-5}$ and is 44 percent smaller and consumes 28 percent less energy per decoded bit.