• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2004.05a
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• pp.106-110
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• 2004

In any large heavy industry like that of ship building, there exist a lot of complications for the arrangement of building blocks optimally for the minimal space consumption. The major problem arises at yard because of laxity in space for arranging the building blocks of ship under construction. A standardized erection sequence diagram is generally available to provide the prioritised erection sequence. This erection sequence diagram serves as the frame work. In order to make a timely erection of the blocks a post plan has to be developed so that the blocks lie in the nearest possible vicinity of the material handling devices while keeping the priority of erection. Therefore, the blocks are arranged in the pre-erection area. This kind of readiness of blocks leads to a very complex problem of space. This arises due to the least available space leading to an urgent need of an availability of intelligent spatial schedule without compromising the rate of production. There exists two critical problems ahead namely, the spatial occupation layout of pre-erection area and the emptying pattern in the spatial vicinity. The block shape is assumed be rectangular. The related input data's are the dates of erection (earliest as well as the latest), geometrical parameters of block available on pre-erection area, slack time and the like.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.41-48
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• 2005

The crosstalk effects that can be observed in the very dee submicron semiconductor chips are due to the coupling capacitances between interconnect lines. The accuracy of the full-chip timing analysis is determined by the accuracy of the estimated propagation delays of cells and interconnects within the chip. This paper presents a CMOS cell driver model and delay calculation algerian capturing the crosstalk effects due to the coupling capacitances. The proposed model and algorithm were implemented in a delay calculation program and used to estimate the propagation delays of the benchmark circuits extracted from a chip layout. We observed that the average discrepancy from HSPICE simulation results is within $1\%$ for the circuits with a victim affected by $0\~10$ aggressors.

• The Journal of Sustainable Design and Educational Environment Research
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• v.11 no.1
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• pp.23-31
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• 2012

The number of school crime has grown continuously for last ten years and its intensity also has reached to serious condition. The concept of CPTED(Crime Prevention through Environmental Design) needs to be focused for improving school environment regarding this context. The exterior space of school environment is variously exposed to school crimes committed by colleague students and also intruders. From the perspective of school CPTED, Natural surveillance as one of the practical strategies requires the micro-scale analysis which clarifies local visibility at each different school exterior space. Thus, the purpose of this research is to develop the analysis method clarifying visibility condition at exterior space of school environment, which supports finding the condition of natural surveillance. The programmed analysis algorithm generated quantitative results clarifying Degree for static visibility and Clustering Coefficient for user tracking visibility. The result of this study produced the analysis method feasible to clarify weak natural surveillance conditions at school exterior spaces. Also, it is expected that the developed analysis method will be used to improve the layout of school exterior space from the perspective of CPTED.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.7
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• pp.140-145
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• 1989

In this paper, we present an effective circuit placement method called SOAP (self-organization assisted placement) for rectilinear or arbitrarily-shaped region arised form the layout of ASIC (application specific integrated circuit). Self-organization is a learning algorithm for neural networks proposed by [1] which adjusts weights of synapses connected to neurons such that topologically close neurons are sensitive to inputs that are physically similar. In SOAP, we obtain a good circuit placement result in arbitrarily-shaped region by replacing the block of circuit and the position (x, y coordinates) of the block with the neuron and the weight pair of synapses connected to the neuron, respectively. This method can also be extended to the circuit placement over the nonplanar surface.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.543-552
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• 1994

Dynamic Time Warp(DTW) needs for iterative calculations and the design of PE cell suitable for the operations is very important. Accordingly, this paper aims at real time recognition design enables large dictionary hardware realization using DTW algorithm. The DTW PE cell separated into three large blocks. "MIN" is the one block for counting accumulated minimum distance. "ADD" block calculates these minimum distances, and "ABS" seeks for the absolute values to the total sum of local distances. Circuit design and verification about the three block have been accomplished, and performed layout '||'&'||' DRC(design rule check) using 1.2 m CMOS N-Well rule base.CMOS N-Well rule base.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.35-46
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• 1999

A derotator VLSI which compensates for the frequency and phase errors of a received signal in digital communication systems was developed employing a CORDIC algorithm. The CORDIC circuit directly rotates the input signal according to the phase error information, thus is much simpler than the conventional derotator architecture which consists of a DDFS (Direct Digital Frequency Synthesizer) and a complex multiplier. Since a derotator needs only small phase error accumulation, a fast direction sequence generation method which exploits the linearity of the arctangent function in small angles is utilized in order to enhance the operating speed. The chip was designed and implemented using a $0.6\mu\textrm{m}$ triple metal CMOS process by the full custom layout method. The whole chip size is $6.8\textrm{mm}^2$ and the maximum operating frequency is 25 MHz.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.11
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• pp.3525-3537
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• 1996

This paper presents a CAD program develpoed on a microcomputer in order to support graphic and computational assessment of ergonomic problems associated with the design of a man-in-cab system. The program is coded to help workspace designers with ergonomic evaluations needed in the design stage. This paper proposed a biomechanical -ergonomic evaluations needed using man and workplace models. The human model is developed to have dimensions obtained from the Korean anthropometric data reported in 1992. Its graphical representation is based on a wire-frame model but, whenever necessary, body segments can be represented by a solid model with hidden line/faces removed and shaded. Workplace models are presented for cabs of the excavator, one of the most popular construction vehicles. A workplace model consists of an operator seat, a steering wheel. two control levers, two pedals, and a control panel. The workplace elements can be modified in their sizes, positions, and orientations by changing the reference point and design parameters. An algorithm for the view test is suggested and loaded to provide a visual evaluaiton of the overall layout of a workplace model.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.31 no.1 s.256
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• pp.43-49
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• 2007

A new electric coil design methodology using the notion of topology optimization is developed. The specific design problem in consideration is to find optimal coil configuration that maximizes the Lorentz force under given magnetic field. Topology optimization is usually formulated using the finite element method, but the novel feature of this method is that no such partial differential equation solver is employed during the whole optimization process. The proposed methodology allows the determination of not only coil shape but also the number of coil turns which is not possible to determine by any existing topology optimization concept and to perform single coil strand identification algorithm. The specific applications are made in the design of two-dimensional fine-pattern focusing coils of an optical pickup actuator. In this method, the concept of equivalent magnetizing current is utilized to calculate the Lorentz force, and the optimal coil configuration is obtained without any initial layout. The method is capable of generating the location and shape of turns of coil. To confirm the effectiveness of the proposed method in optical pickup applications, design problems involving multipolar permanent magnets are considered.

• Journal of the Semiconductor & Display Technology
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• v.9 no.1
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• pp.67-71
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• 2010

Head up display’s cooling system is auto-diagnosed resulting from the external environment. The quantity of heat depending on this Head up display’s cooling system layout determines the speed of FAN for system cooling. In other words, a system’s heat quantity is planned through the air density depending on altitude, the amount of wind in air depending on FAN control condition, and the algorithm that is proportional to delta temperature. To detect the altitude, we use the criteria of delta T, which is determined by the subtracted value of LED junction temperature, and atmospheric temperature that is recorded on the Head up display system. Depending on the classification of delta T value, the altitude section is determined. While we can use GPS as the tool to detect the altitude, we should predict the change of the air density as the altitude alters, and should not just measure the altitude. And the value of delta T is used as the criterion of detecting the altitude for increasing the cooling efficiency of the car’s inner Head up display system with reflecting the speed of the FAN dependent upon the air density. In our theory, altitude is depending on the value of delta T and stabilizing or maintaining the system’s temperature by changing FAN’s rpm depending on determined value of altitude.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.8
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• pp.639-647
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• 1990

Dynamic time warp(DTW) needs for interative calculations and the design of PE cell suitable for the operations is very important. Accordingly, this paper aims at the real time recognition design which enables large dictionary hardware realization using DTW algorithm. The DTW PE cell is seperated into three large blocks. "MIN" is the one block for counting accumulated minimum distance, "ADD" block calculates these minimum distances, and "ABS" seeks for the absolute values to the total sum of local distances. We have accomplisehd circuit design and verification for the MIN blocks, and performed MIN layout and DRC(design rule check) using 3um CMOS N-Well rule base.ing 3um CMOS N-Well rule base.