• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.36 no.3
• /
• pp.226-232
• /
• 2023

As a potential alternative to flash memory, HfO₂/Al₂O₃ stacks appear to be a viable option as charge capture layers in charge trapping memories. The paper undertakes a review of HfO₂/Al₂O₃ stacks as charge trapping layers, with a focus on comparing the number, thickness, and post-deposition heat treatment and γ-ray and white x-ray treatment of such stacks. Compared to a single HfO₂ layer, the memory window of the 5-layered stack increased by 152.4% after O₂ annealing at ±12 V. The memory window enlarged with the increase in number of layers in the stack and the increase in the Al/Hf content in the stack. Furthermore, our comparison of the treatment of HfO₂/Al₂O₃ stacks with varying annealing temperatures revealed that an increased annealing temperature resulted in a wider storage window. The samples treated with O₂ and subjected to various γ radiation intensities displayed superior resistance. and the memory window increased to 12.6 V at ±16 V for 100 kGy radiation intensity compared to the untreated samples. It has also been established that increasing doses of white x-rays induced a greater number of deep defects. The optimization of stacking layers along with post-deposition treatment condition can play significant role in extending the memory window.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.240-240
• /
• 2010

A multiple alloy metal nano-dots memory using FN tunneling was investigated in order to confirm its structural possibility for future flash memory. In this work, a multiple FePt nano-dots device with a high work function (~5.2 eV) and extremely high dot density (${\sim}\;1.2{\times}10^{13}/cm^2$) was fabricated. Its structural effect for multiple layers was evaluated and compared to one with a single layer in terms of the cell characteristics and reliability. We confirm that MOS capacitor structures with 2-4 multiple FePt nano-dot layers provide a larger threshold voltage window and better retention characteristics. Furthermore, it was also revealed that several process parameters for block oxide and inter-tunnel oxide between the nano-dot layers are very important to improve the efficiency of electron injection into multiple nano-dots. From these results, it is expected that a multiple FePt nano-dots memory using Fowler-Nordheim (FN)-tunneling could be a candidate structure for future flash memory.

• Journal of Korea Society of Industrial Information Systems
• /
• v.14 no.2
• /
• pp.72-80
• /
• 2009

In this parer, we propose a hardware abstraction architecture(HAA) for low cost flash memories that can be applicable to wireless sensor nodes. The proposed HAA consists of three layers. The three layers are 1) HHL(Hardware Interlace Layer), HAL(Hardware Adaption Layer), and HPL(Hardware Presentation Layer), where HIL provides a platform independent interlace to applications of upper layers, HAL performs hardware resource management, program status control, and generation of logical instructions as main core of the HAA, and HPL initializes hardware and communicates data between MCU and flash memory. We implemented our HAA on AT45DB flash memory, and the HAA used 4,384 bytes program memory and 195 bytes data memory respectively. Since the proposed HAA is composed of well defined three layers and shows a low utilization of memory, it can provides a high efficiency in terms of flexibility, scalability, and re-usability, and thus the HAA is well suited for wireless sensor nodes.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.10
• /
• pp.865-870
• /
• 2003

The MFIS (Metal-Ferroelectric-Insulator-Semiconductor) capacitors were fabricated using a metalorganic decomposition method. Thin layers of CeO$_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the CeO$_2$ layer. The morphology of films and the interface structures of the BLT and the CeO$_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 2.82 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.1044-1046
• /
• 2009

Here we report the architecture for a non-volatile n-type memory paper field-effect transistor. The device is built using the hybrid integration of natural cellulose fibers (pine and eucalyptus fibers embedded in an ionic resin), which act simultaneously as substrate and gate dielectric, with amorphous GIZO and IZO oxides as gate and channel layers, respectively. This is complemented by the use of continuous patterned metal layers as source/drain electrodes.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.5
• /
• pp.737-748
• /
• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.5
• /
• pp.439-444
• /
• 2005

We investigated the structural and electrical properties of BLT films grown on Si covered with $ZrO_{2}$ buffer layer. The BLT thin film and $ZrO_{2}$ buffer layer were fabricated using a metalorganic decomposition method. The electrical properties of the MFIS structure were investigated by varying thickness of the $ZrO_{2}$ layer. AES and TEM show no interdiffusion and reaction that suppressed using the $ZrO_{2}$ film as a buffer layer The width of the memory window in the C-V curves for the MFIS structure decreased with increasing thickness of the $ZrO_{2}$ layer. It is considered that the memory window width of MFIS is not affected by remanent polarization. Leakage current density decreased by about four orders of magnitude after using $ZrO_{2}$ buffer layer. The results show that the $ZrO_{2}$ buffer layers are prospective candidates for applications in MFIS-FET memory devices.

• The Research Journal of the Costume Culture
• /
• v.27 no.1
• /
• pp.1-10
• /
• 2019

Firefighters wear Personal Protective Equipment (PPE) for protection from environmental hazards. However, due to the layers of protective functions, the PPE inevitably adds excessive weight, bulkiness, and thermal stress to firefighters. This study investigated the adverse impact of wearing PPE as an occupational stressor on the firefighter's cognitive functioning. Twenty-three firefighters who had been involved in firefighting at least for 1 year were recruited. The overall changing trend in the firefighter's cognitive functioning (short-term memory, long-term memory, and inductive reasoning) was measured by the scores of three standardized cognitive tests at the baseline and the follow-up, after participating in a moderate-intensity physical activity, wearing a full ensemble of the PPE. The study findings evinced the negative impact of the PPE on the firefighter's cognitive functioning, especially in short-term memory and inductive reasoning. No significant influence was found on the firefighter's long-term memory. The results were consistent when the participant's age and BMI were controlled. The outcomes of the present study will not only fill the gap in the literature, but also provide critical justification to stakeholders, including governments, policymakers, academic communities, and industry, for such efforts to improve human factors of the firefighter's PPE by realizing the negative consequences of the added layers and protective functions on their occupational safety. Study limitations and future directions were also discussed.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.298.1-298.1
• /
• 2016

Two-dimensional materials have been received significant interest after the discovery of graphene due to their fascinating electronic and optical properties for the application of novel devices. However, graphene lack of certain bandgap which is essential requirement to achieve high performance field-effect transistors. Analogous to graphene materials, molybdenum disulfide ($MoS_2$) as one of transition-metal dichalcogenides family presents considerable bandgap and exhibits promising physical, chemical, optical and mechanical properties. Here we studied nonvolatile memory based on $MoS_2$ which is grown by chemical vapor deposition (CVD) method. $MoS_2$ growth was taken on $1.5{\times}1.5cm^2$ $SiO_2$/Si-substrate. The samples were analyzed by Raman spectroscopy, atomic force microscopy and X-ray photoelectron spectroscopy. Current-voltage (I-V) characteristic was carried out HP4156A. The CVD-$MoS_2$ was analyzed as few layers and 2H-$MoS_2$ structure. From I-V measurement for two metal contacts on CVD-$MoS_2$ sample, we found typical resistive switching memory effect. The device structures and the origin of nonvolatile memory effect will be discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.415-416
• /
• 2009

The tunnel barrier engineered charge trap flash (TBE-CTF) non-volatile memory using CRESTED tunneling barrier was fabricated by stacking thin $Si_3N_4$ and $SiO_2$ dielectric layers. Moreover, high-k based $HfO_2$ charge trap layer and $Al_2O_3$ blocking layer were used for further improvement of the NVM (non-volatile memory) performances. The programming/erasing speed, endurance and data retention of TBE-CTF memory was evaluated.