• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.414-415
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• 2005

A solar cell is an element to transform the solar light energy into the electric energy in a moment. The single crystal element of high quality on which many studies were conducted in the past has a high efficiency of energy transformation, but its price competitiveness is so poor that it has failed to be popularized However, recently, in terms of an environment-friendly alternative energy, studies on applicability of the polycrystal solar cell have been actively under way. Among subject substances for such solar cell, $CuInSe_2$ has several good physical properties so that the greatest attention is paid to it as an optical absorption layer material for a low-cost solar cell of high efficiency. In order to manufacture the $CuInSe_2$ compound thin film, the unit element was deposited by using the sputtering method and the evaporation method and the heat treatment process was used in an electric furnace. Thereby, we intended to get a single-phase $CuInSe_2$ compound thin film.

• Journal of Electrochemical Science and Technology
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• v.10 no.3
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• pp.335-343
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• 2019

In this study, $Sr_2Ni_{1.8}Mo_{0.2}O_{6-{\delta}}$ (SNM) with a double perovskite structure was investigated as an alternative anode for use in the $CH_4$ fuel in solid oxide fuel cells. SNM demonstrates a double perovskite phase over $600^{\circ}C$ and marginal crystallization at higher temperatures. The Ni nanoparticles were exsolved from the SNM anode during the fabrication process. As the SNM anode demonstrates poor electrochemical and electro-catalytic properties in the $H_2$ and $CH_4$ fuels, it was modified by applying a samarium-doped ceria (SDC) coating on its surface to improve the cell performance. As a result of this SDC modification, the cell performance improved from $39.4mW/cm^2$ to $117.7mW/cm^2$ in $H_2$ and from $15.9mW/cm^2$ to $66.6mW/cm^2$ in $CH_4$ at $850^{\circ}C$. The mixed ionic and electronic conductive property of the SDC provided electrochemical oxidation sites that are beyond the triple boundary phase sites in the SNM anode. In addition, the carbon deposition on the SDC thin layer was minimized due to the SDC's excellent oxygen ion conductivity.

• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.250-254
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• 2021

A highly sensitive and selective non-dispersive infrared (NDIR) carbon dioxide gas sensor requires achieving high transmittance and narrow full width at half maximum (FWHM), which depends on the interface of the optical filter for precise measurement of carbon dioxide concentration. This paper presents the design, simulation, and fabrication of a Fabry-Perot filter based on a distributed Bragg reflector (DBR) for a low-cost NDIR carbon dioxide sensor. The Fabry-Perot filter consists of upper and lower DBR pairs, which comprise multilayered stacks of alternating high- and low-index thin films, and a cavity layer for the resonance of incident light. As the number of DBR pairs inside the reflector increases, the FWHM of the transmitted light becomes narrower, but the transmittance of light decreases substantially. Therefore, it is essential to analyze the relationship between the FWHM and transmittance according to the number of DBR pairs. The DBR is made of silicon and silicon dioxide by RF magnetron sputtering on a glass wafer. After the optimal conditions based on simulation results were realized, the DBR exhibited a light transmittance of 38.5% at 4.26 ㎛ and an FWHM of 158 nm. The improved results substantiate the advantages of the low-cost and minimized process compared to expensive commercial filters.

• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.267-272
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• 2021

In this study, Ag was deposited to investigate its applicability as a surface-enhanced Raman scattering substrate after forming a grass-type black silicon structure through maskless reactive ion etching. Grass-structured black silicon with heights of 2 - 7 ㎛ was formed at radio-frequency (RF) power of 150 - 170 W. The process pressure was 250 mTorr, the O₂/SF₆ gas ratio was 15/37.5, and the processing time was 10 - 20 min. When the processing time was increased by more than 20 min, the self-masking of Si_xO_yF_z did not occur, and the black silicon structure was therefore not formed. Raman response characteristics were measured based on the Ag thickness deposited on a black silicon substrate. As the Ag thickness increased, the characteristic peak intensity increased. When the Ag thickness deposited on the black silicon substrate increased from 40 to 80 nm, the Raman response intensity at a Raman wavelength of 1507 / cm increased from 8.2 × 10³ to 25 × 10³ cps. When the Ag thickness was 150 nm, the increase declined to 30 × 10³ cps and showed a saturation tendency. When the RF power increased from 150 to 170 W, the response intensity at a 1507/cm Raman wavelength slightly increased from 30 × 10³ to 33 × 10³ cps. However, when the RF power was 200 W, the Raman response intensity decreased significantly to 6.2 × 10³ cps.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.16 no.1
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• pp.96-101
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• 2017

We have developed a compact desktop-sized nanopatterning system driven by the Roll-to-Roll (R2R) nanoimprinting (NIL) principle. The system realizes the continuous and high-speed stamping of various nanoscale patterns on a large-area flexible substrate without resorting to ponderous and complicated instruments. We first lay out the process principle based on continuous NIL on a UV-curable resin layer using a flexible nanopatterned mold. We then create conceptual and specific designs for the system by focusing on two key processes, imprinting and UV curing, which are performed in a continuous R2R fashion. We build a system with essential components and optimized modules for imprinting, UV curing, and R2R conveying to enable simple but effective nanopatterning within the desktop volume. Finally, we demonstrate several nanopatterning results such as nanolines and nanodots, which are obtained by operating the built desktop R2R NIL system on transparent and flexible substrates. Our system may be further utilized in the scalable fabrication of diverse flexible nanopatterns for many functional applications in optics, photonics, sensors, and energy harvesters.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.2
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• pp.99-104
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• 2020

In this study, we fabricated a metamorphic high-electron-mobility transistor (mHEMT) device with a T-type gate structure for the implementation of W-band monolithic microwave integrated circuits (MMICs) and investigated its characteristics. To fabricate the mHEMT device, a recess process for etching of its Schottky layer was applied before gate metal deposition, and an e-beam lithography using a triple photoresist film for the T-gate structure was employed. We measured DC and RF characteristics of the fabricated device to verify the characteristics that can be used in W-band MMIC design. The mHEMT device exhibited DC characteristics such as a drain current density of 747 mA/mm, maximum transconductance of 1.354 S/mm, and pinch-off voltage of -0.42 V. Concerning the frequency characteristics, the device showed a cutoff frequency of 215 GHz and maximum oscillation frequency of 260 GHz, which provide sufficient performance for W-band MMIC design and fabrication. In addition, active and passive modeling was performed and its accuracy was evaluated by comparing the measured results. The developed mHEMT and device models could be used for the fabrication of W-band MMICs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.3
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• pp.42-51
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• 1981

Boron was predeposited into p (100) Si wafer at 94$0^{\circ}C$ for 60minutes to make the back surface field. High tempreature diffusion process at 1145$^{\circ}C$ for 3 hours was immediately followed without removing boron glass to obtain high surface concentration Back boron was annealed at 110$0^{\circ}C$ for 40minutes after boron glass was removed. N+ layer was formed by predepositing with POCI3 source at 90$0^{\circ}C$ for 7~15 minutes and annealed at 80$0^{\circ}C$ for 60min1es under dry Of ambient. The triple metal layers were made by evaporating Ti, Pd, Ag in that order onto front and back of diffused wafer to form the front grid and back electrode respectively. Silver was electroplated on front and back to increase the metal thickness form 1~2$\mu$m to 3~4$\mu$m and the metal electrodes are alloyed in N2 /H2 ambient at 55$0^{\circ}C$ and followed by silicon nitride antireflection film deposition process. Under artificial illumination of 100mW/$\textrm{cm}^2$ fabricated N+PP+ cells showed typically the open circuit voltage of 0.59V and short circuit current of 103 mA with fill factor of 0.80 from the whole cell area of 3.36$\textrm{cm}^2$. These numbers can be used to get the actual total area(active area) conversion efficiency of 14.4%(16.2%) which has been improved from the provious N+P cell with 11% total area efficiency by adding P+ back.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.478-478
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• 2012

Recently, there are many researches in order to increase the deposition rate (D/R) and improve film uniformity and quality in the deposition of microcrystalline silicon thin film. These two factors are the most important issues in the fabrication of the thin film solar cell, and for the purpose of that, several process conditions, including the large area electrode (more than 1.1 X 1.3 (m2)), higher pressure (1 ~ 10 (Torr)), and very high frequency regime (VHF, 40 ~ 100 (MHz)), have been needed. But, in the case of large-area capacitively coupled discharges (CCP) driven at frequencies higher than the usual RF (13.56 (MHz)) frequency, the standing wave and skin effects should be the critical problems for obtaining the good plasma uniformity, and the ion damage on the thin film layer due to the high voltage between the substrate and the bulk plasma might cause the defects which degrade the film quality. In this study, we will propose the new concept of the large-area multi-electrode (a new multi-electrode concept for the large-area plasma source), which consists of a series of electrodes and grounds arranged by turns. The experimental results with this new electrode showed the processing performances of high D/R (1 ~ 2 (nm/sec)), controllable crystallinity (~70% and controllable), and good uniformity (less than 10%) at the conditions of the relatively high frequency of 40 MHz in the large-area electrode of 280 X 540 mm2. And, we also observed the SEM images of the deposited thin film at the conditions of peeling, normal microcrystalline, and powder formation, and discussed the mechanisms of the crystal formation and voids generation in the film in order to try the enhancement of the film quality compared to the cases of normal VHF capacitive discharges. Also, we will discuss the relation between the processing parameters (including gap length between electrode and substrate, operating pressure) and the processing results (D/R and crystallinity) with the process condition map for ${\mu}c$-Si:H formation at a fixed input power and gas flow rate. Finally, we will discuss the potential of the multi-electrode of the 3.5G-class large-area plasma processing (650 X 550 (mm2) to the possibility of the expansion of the new electrode concept to 8G class large-area plasma processing and the additional issues in order to improve the process efficiency.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.120-120
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• 2011

Graphene is a carbon based material and it has great potential of being utilized in various fields such as electronics, optics, and mechanics. In order to develop graphene-based logic systems, graphene field-effect transistor (GFET) has been extensively explored. GFET requires supporting devices, such as volatile memory, to function in an embedded logic system. As far as we understand, graphene has not been studied for volatile memory application, although several graphene non-volatile memories (GNVMs) have been reported. However, we think that these GNVM are unable to serve the logic system properly due to the very slow program/read speed. In this study, a GVM based on the GFET structure and using an engineered graphene channel is proposed. By manipulating the deposition condition, charge traps are introduced to graphene channel, which store charges temporarily, so as to enable volatile data storage for GFET. The proposed GVM shows satisfying performance in fast program/erase (P/E) and read speed. Moreover, this GVM has good compatibility with GFET in device fabrication process. This GVM can be designed to be dynamic random access memory (DRAM) in serving the logic systems application. We demonstrated GVM with the structure of FET. By manipulating the graphene synthesis process, we could engineer the charge trap density of graphene layer. In the range that our measurement system can support, we achieved a high performance of GVM in refresh (>10 ${\mu}s$) and retention time (~100 s). Because of high speed, when compared with other graphene based memory devices, GVM proposed in this study can be a strong contender for future electrical system applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.14-23
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• 2010

This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.