• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.96-106
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• 1996

One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.78-88
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• 1994

The electrical properties of TiM/TiSi$_{2}$ bilayer formed by rapid thermal anneal in NH$_{3}$ ambient after the Ti film is deposited on silicon cubstrate are investigated. N$^{+}$ contact resistance slightly increases with increasing annealing temperature with P$^{+}$ contact resistance decreases. The contact resistance of N$^{+}$ contance was less than 24[.OMEGA.] but P$^{+}$ thatn that of N$^{+}$ contact but the leakage current indicates degradation of the contact at high annealing temperature for both N$^{+}$ and contacts. The leakage current of N$^{+}$ Junction was less than 0.06[fA/${\mu}m^{2}$] but P$^{+}$ contact was 0.11-0.15[fA/${\mu}m^{2}$]. The junction breakdown voltage for N$^{+}$ junction remains contant with increasing annealing temperature while P$^{+}$ junction slightly decreases. The Electrical properties of a two step annealing are better than that of one step annealing. The Tin/TiSi$_{2}$ bilayer formed by RTA in NH$_{3}$ ambient reveals good electrical properties to be applicable at ULSI contact.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.2
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• pp.170-177
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• 1992

Contact resistance and contact leakage current of the Al/TiSiS12T/Si system are investigated for NS0+T and PS0+T junctions. SALICIDE (Self Aligned Silicide) process was used to make the Al/TiSiS12T/Si system. Titanium disilicide is one of the most common silicides because of its thermal stability, ability to form selective formation and low resistivity. In this paper, RTA temperature effect and Junction implant dose effect were evaluated to characterize contact resistance and contact leakage current. The TiSiS12T contact resistance to NS0+T silicon is lower than that to PS0+T silicon, and TiSiS12T of contact leakage current to NS0+T silicon is lower than that to PS0+T silicon. Contact resistance and contact leakage current of the Al/TiSiS12T/Si system by this method were possible for VLSI application.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.359-362
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• 2016

In the PV (Photovoltaic) power system, a junction box collects the DC voltage generated from the PV module and transfers it to the PCS (power conditioning system). The junction box prevents damage caused by the voltage difference between the serially connected PV modules and provides convenience while repairing or inspecting the PV array. In addition, the junction box uses the diode to protect modules from the inverse current when the PV power system and electric power system are connected for use. However, by using the reverse blocking diode, heat is generated within the junction box while generating electric power, which decreases the generating efficiency, and causes short circuit and electric leakage. In this research, based on the purpose of improving the performance of the PV module by decreasing the heat generation within the junction box, a junction box with a built-in bypass circuit was designed/manufactured so that a certain capacity of current generated from the PV module does not run through the reverse blocking diode. The manufactured junction box was used to compare the electric power and heating power generated when the circuit was in the bypass/non-bypass modes. It was confirmed that the electric power loss and heat generation indicated a decrease when the circuit was in the bypass mode.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.344-345
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• 2012

The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

• Progress in Superconductivity
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• v.4 no.1
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• pp.59-63
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• 2002

10-V Josephson junction array arranged in 8 parallel stripline paths was fabricated using self-aligning and reactive ion etching techniques. These techniques were introduced in detail with aim of obtaining high-quality junctions. The array has 18,184 Josephson junctions with the area of $12\mu\textrm{m}$$\times$$38\mu\textrm{m}$. The gap voltage and minimum critical current density were about 2.7 ㎷ and ／$23 A\textrm{cm}^2$, respectively. And the critical current density and leakage current at 5 volt were about 27 $A／\textrm{cm}^2$ and $5\mu\textrm{A}$, respectively When operated in the frequency range of 76-88 ㎓, the away generated constant voltage steps up to 14-19 V. The step size near 10-V was more than 7 $\mu\textrm{A}$.

• Journal of the Korean Society of Radiology
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• v.3 no.1
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• pp.11-15
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• 2009

In this study, the basic research verifying possibility of applications as radiology image sensor in Digital Radiography was performed, the radiology image sensor was fabricated using a multi-layer technique to decrease dark current. High efficiency materials in substitution for Amorphous Selenium(a-Se) have been studied as a direct method of imaging detector in Digital Radiography to decrease dark current by using PN junction or Hetero junction already used as solar cell, semiconductor. Particle-In -Binder method is used to fabricate radiology image sensor because it has a lot of advantages such as fabrication convenient, high yield, suitability for large area sensor. But high leakage current is one of main problem in Particle-In -Binder method. To make up for the weak points, multi-layer technique is used, and it is considered that high efficient digital radiation sensor can be fabricated with easy and convenient process. In this study, electrical properties such as leakage current, sensitivity, signal linearity is measured to evaluate multi-layer radiation sensor material.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.163-166
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• 2004

모바일향 90nm DRAM을 개발하기 위하여 비대칭 채널 구조를 갖는 Recess Channel Array Transistor (RCAT)로 cell transistor를 구현하였다. DRAM cell transistor에서 junction leakage current 증가는 DRAM retention time 열화에 심각한 영향을 미치는 요인으로 알려져 있으며, DRAM의 minimum feature size가 점점 감소함에 따라 short channel effect의 영향으로 junction leakage current는 더욱 더 증가하게 된다. 본 실험에서는 short channel effect의 영향에 의한 junction leakage current를 감소시키기 위하여 Recess Channel Array Transistor를 도입하였고, cell transistor의 채널 영역을 비대칭으로 형성하여 data retention time을 증가시켰다. 비대칭 채널 구조을 이용하여 Recess Channel Array Transistor를 구현한 결과, sub-threshold 특성과 문턱전압, Body effect, 그리고, GIDL 특성에는 큰 유의차가 보이지 않았고, I-V특성인 드레인 포화전류(IDS)는 대칭 채널 구조인 transistor 대비 24.8% 정도 증가하였다. 그리고, data retention time은 2배 정도 증가하였다. 본 실험에서 얻은 결과는 향후 저전압 DRAM 개발과 응용에 상당한 기여를 할 것으로 기대된다.

• Transactions on Electrical and Electronic Materials
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• v.17 no.1
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• pp.21-24
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• 2016

A junction box used in a 3 kW photovoltaic power generation system plays a role in collecting and supplying the direct current voltage produced by photovoltaic modules to an inverter. It is also used for facilitating maintenance checks and protecting the module and inverter by keeping the voltage constant. As for the junction box, using it in a parallel connection creates a difference between the setup modules. In order to compensate, an inverse voltage diode is used. But the high-power created through the solar generator can be delivered to the inverter through the inverter regularly. Therefore, a component can break down due to excess heat. And consequently short circuits and electric leakage occurs. In this study, using a junction box that enabled the bypass of high electric power, it was possible to reduce heat generation by approximately 35℃ when compared to a standard junction box.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.176-182
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• 1992

t-Stress and junction leakage current characteristics of CVD-tungsten have been investigated. Stressversus continuous annealing temperature plot. shows hysteresis curve where the stress level of the cooling curveis higher than that of the heating curve. It is found that the thermal and intrinsic stress of tungsten film depositedby SiH4 reduction is higher than that by Hz reduction.The tungsten film deposited by SiHl reduction is in the tensile stress state below 700"Cnd the stress ofthe film decreses with increasing annealing temperature. The stress state changes into compressive stress atabout 700"Cnd the compressive stress increases rapidly with increasing temperature.Leakage current of the n+/p diode increases rapidly especially in the range of 400-450$^{\circ}$C with increasingdeposition temperature of the CVD-W by SiH4 reduction, which is due to the Si consumption by W encroachment.On the other hand leakage current of the n+/p diode slightly increases with increasing SiH4/WF6 ratio.h increasing SiH4/WF6 ratio.