• Journal of electromagnetic engineering and science
• /
• v.12 no.4
• /
• pp.254-259
• /
• 2012

This paper presents a closely spaced two-element folded-dipole-driven quasi-Yagi array with low mutual coupling between adjacent elements. The antenna utilizes a T-junction power divider as the feeding network, with an input impedance of $50{\Omega}$. A microstrip-stub is added to the ground plane in the middle of the two elements to improve the mutual coupling characteristics. The folded dipole driver is connected to a $50{\Omega}$ microstrip line via a broadband microstrip-to-coplanar stripline transition with a quarter radial stub. A mutual coupling of less than -22 dB is measured between two folded-dipole-driven quasi-Yagi antennas with a center-to-center spacing of 30 mm ($0.55{\lambda}_0$ at 5.5 GHz). The proposed quasi-Yagi array yields a measured bandwidth of 4.75~6.43 GHz for the -10 dB reflection coefficient and a gain of 6.14~7.12 dBi within the bandwidth range.

• Progress in Superconductivity
• /
• v.9 no.1
• /
• pp.56-61
• /
• 2007

The most recent improvement in the 10 V array system was carried out with focusing on noise reduction. We have evaluated the uncertainty of the 10 V Josephson array system after the improvement. The uncertainty evaluation of 10 V standard included a comparison with a programmable Josephson array system at 1 V. Every contribution to the measurement uncertainty was evaluated in the level of $10^{-10}$. The estimated combined uncertainty was found to be approximately $10^{-9}$ at 10 V, which was limited only by the indirect verifying method. In the near future, a direct comparison with another 10 V Josephson voltage standard is expected to be carried out to provide more accurate uncertainty evaluation for the KRISS Josephson voltage standard.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.1
• /
• pp.30-37
• /
• 2006

In this article, we evaluated the structural merits and the validity of a partially insulated MOSFET (PiFET) through the fabrication of prototype transistors and an 80 nm 512M DDR DRAM with partially-insulated cell array transistors (PiCATs). The PiFETs showed the outstanding short channel effect immunity and off-current characteristics over the conventional MOSFET, resulting from self-induced halo region, self-limiting SID shallow junction, and reduced junction area due to PiOX layer formation. The DRAM with PiCATs also showed excellent data retention time. Thus, the PiFET can be a promising alternative for ultimate scaling of planar MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.5 no.2
• /
• pp.102-106
• /
• 2005

A low dark current CMOS image sensor (CIS) pixel without any process modification is developed. Dark current is mainly generated at the interface region of shallow trench isolation (STI) structure. Proposed pixel reduces the dark current effectively by separating the STI region from the photodiode junction using simple layout modification. Test sensor array that has both proposed and conventional pixels is fabricated using 0.18 m CMOS process and the characteristics of the sensor are measured. The result shows that the dark current of the proposed pixel is 0.93fA/pixel that is two times lower than the conventional design.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.6
• /
• pp.90-98
• /
• 1996

We have evaluated the theoretical conversion loss and noise temperature of mixer using the quantum mixer theory and the method to determine the embedding impedance of waveguide-type mixer mount. At fixed backshort position of the mixer, the calculated SSB mixer conversion loss and mixer noise temperature are 5 dB and 10K within frequency range form 85 GHz to 115 GHz, respectively. The SIS mixer has been developed by using through on the calculated rsutls to observe cosmic radio waves. SIS junction of mixer is Nb/Al-AlOx/Nb and it consists of four series array. Area of each of junction is about 2.5${\mu}m^{2}$. The average receiver noise temperature of manufactured receiver with this mixer is about 30 K(DSB). The receiver noise temperature is much lower than that of receiver with a mixer using mechanical tuning backshort.

• Journal of the Semiconductor & Display Technology
• /
• v.16 no.1
• /
• pp.65-69
• /
• 2017

This paper presents a Technology-CAD (TCAD) simulation of the characteristics of crystalline Si pillar array solar cells. The junction depth and the surface concentration of the solar cells were optimized to obtain the targeted sheet resistance of the emitter region. The diffusion model was determined by calibrating the emitter doping profile of the microscale silicon pillars. The dimension parameters determining the pillar shape, such as width, height, and spacing were varied within a simulation window from ${\sim}2{\mu}m$ to $5{\mu}m$. The simulation showed that increasing pillar width (or diameter) and spacing resulted in the decrease of current density due to surface area loss, light trapping loss, and high reflectance. Although increasing pillar height might improve the chances of light trapping, the recombination loss due to the increase in the carrier's transfer length canceled out the positive effect to the photo-generation component of the current. The silicon pillars were experimentally formed by photoresist patterning and electroless etching. The laboratory results of a fabricated Si pillar solar cell showed the efficiency and the fill factor to be close to the simulation results.

• New & Renewable Energy
• /
• v.5 no.4
• /
• pp.34-37
• /
• 2009

Using six SMD(surface mount device) type AlGaAs/GaAs single junction solar cells connected in series, a power source was fabricated for a white GaN LED. The electrical properties of the power source was measured and analyzed under one sun (100mW/$cm^2$) and various indoor light (300 - 900 lux) conditions. Under 600 lux indoor light condition, output power was 17.06 ${\mu}W$ and it was 30.75 ${\mu}W$ under 900 lux indoor light condition. Using the fabricated solar cell power supply, we have turned on the white GaN LED. It was worked well under 15 ${\mu}W$(at 480 lux) power supplied from solar cell array. This kind of solar cell power supply can be used as a power source for ubiquitous sensor network (USN).

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.533-536
• /
• 1998

The electrical characteristics of NMOSFETs with asymmetrical source/drain regions have been expermentally investigated using test devices fabricated by $0.35\mu\textrm{m}$ CMOS technology. The performance degradation for asymmetric transistor and its causes are analyzed. The parasitic resistances, such as series resistance of active regions and silicide junction contact resistance, are distributed in parallel along the channel. Depending on source/drain geometry, the array of those resistances is changed, that results the various electrical properties.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.86-86
• /
• 2012

The new approaches for silicon solar cell of new concept have been actively conducted. Especially, solar cells with wire array structured radial p-n junctions has attracted considerable attention due to the unique advantages of orthogonalizing the direction of light absorption and charge separation while allowing for improved light scattering and trapping. One-dimenstional semiconductor nano/micro structures should be fabricated for radial p-n junction solar cell. Most of silicon wire and/or pillar arrays have been fabricated by vapour-liquid-solid (VLS) growth because of its simple and cheap process. In the case of the VLS method has some weak points, that is, the incorporation of heavy metal catalysts into the growing silicon wire, the high temperature procedure. We have tried new approaches; one is electrochemical etching, the other is noble metal catalytic etching method to overcome those problems. In this talk, the silicon pillar formation will be characterized by investigating the parameters of the electrochemical etching process such as HF concentration ratio of electrolyte, current density, back contact material, temperature of the solution, and large pre-pattern size and pitch. In the noble metal catalytic etching processes, the effect of solution composition and thickness of metal catalyst on the etching rate and morphologies of silicon was investigated. Finally, radial p-n junction wire arrays were fabricated by spin on doping (phosphor), starting from chemical etched p-Si wire arrays. In/Ga eutectic metal was used for contact metal. The energy conversion efficiency of radial p-n junction solar cell is discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.440-440
• /
• 2009

Semiconductor nanowires offer exciting possibilities as components of solar cells and have already found applications as active elements in organic, dye-sensitized, quantum-dot sensitized, liquid-junction, and inorganic solid-state devices. Among many semiconductors, silicon is by far the dominant material used for worldwide photovoltaic energy conversion and solar cell manufacture. For silicon wire to be used for solar device, well aligned wire arrays need to be fabricated vertically or horizontally. Macroscopic silicon wire arrays suitable for photovoltaic applications have been commonly grown by the vapor-liquid-solid (VLS) process using metal catalysts such as Au, Ni, Pt, Cu. In the case, the impurity issues inside wire originated from metal catalyst are inevitable, leading to lowering the efficiency of solar cell. To escape from the problem, the wires of purity of wafer are the best for high efficiency of photovoltaic device. The fabrication of wire arrays by the electrochemical etching of silicon wafer with photolithography can solve the contamination of metal catalyst. In this presentation, we introduce silicon wire arrays by electrochemical etching method and then fabrication methods of radial p-n junction wire array solar cell and the various merits compared with conventional silicon solar cells.