• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.87-95
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• 2013

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

• Aerospace Engineering and Technology
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• v.3 no.2
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• pp.104-115
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• 2004

In this study, contains Design and Simulation data for Tone filter applied to the KSLV-1 FTS Receiver. Received Signal contains unwanted Noise and Jitter which should be eliminated by any kind of filters. In the design of KSLV-1 FTS Receiver, two different type of filters are used. One is Low-Pass Filter for rejecting high order harmonics and another is Tone Filter for sorting pure original signal in the mixed demodulate Signals. For the purpose of this development, various kinds of filter are studied and simulated for finding adequate type of filter.