• Clean Technology
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• v.29 no.4
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• pp.255-261
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• 2023

Power semiconductors are semiconductors used for power conversion, transformation, distribution, and control. Recently, the global demand for high-voltage power semiconductors is increasing across various industrial fields, and optimization research on high-voltage IGBT components is urgently needed in these industries. For high-voltage IGBT development, setting the resistance value of the wafer and optimizing key unit processes are major variables in the electrical characteristics of the finished chip. Furthermore, the securing process and optimization of the technology to support high breakdown voltage is also important. Etching is a process of transferring the pattern of the mask circuit in the photolithography process to the wafer and removing unnecessary parts at the bottom of the photoresist film. Ion implantation is a process of injecting impurities along with thermal diffusion technology into the wafer substrate during the semiconductor manufacturing process. This process helps achieve a certain conductivity. In this study, dry etching and wet etching were controlled during field ring etching, which is an important process for forming a ring structure that supports the 3.3 kV breakdown voltage of IGBT, in order to analyze four conditions and form a stable body junction depth to secure the breakdown voltage. The field ring ion implantation process was optimized based on the TEG design by dividing it into four conditions. The wet etching 1-step method was advantageous in terms of process and work efficiency, and the ring pattern ion implantation conditions showed a doping concentration of 9.0E13 and an energy of 120 keV. The p-ion implantation conditions were optimized at a doping concentration of 6.5E13 and an energy of 80 keV, and the p+ ion implantation conditions were optimized at a doping concentration of 3.0E15 and an energy of 160 keV.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.56-59
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• 2000

In this paper, we have made a comparison between secondary ion mass spectroscopy(SIMS) data by the 5kcV-15keV boron implantation and computer simulation results. In order to make electrical activation of implanted carriers, thermal annealing are carried out by RTP method for 30s at 1000$^{\circ}C$ Two dimensional doping concentration distribution from different mask dimensions under inert gas annealing, dry-, and wet-oxidation condition were calculated and simulated with microtec simulator.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.557-560
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• 1998

We previously developed and presented the 3D ion implantation simulation code, TRICSI. In this paper, we performed the multiple implants into (100) silicon substrate with our recently enhanced version. Our results for the multiple implants were compared with the previously published SIMS data and obtained the good agreements. In this paper the channeling behaviour of implanted impurity and the damage accumulation are analyzed and discussed in the simple 3D structure, named the Hole structure which has a rectangular implant window.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.266-269
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• 2000

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance and leakage tungsten bit-line process with various RTP(Rapid Thermal Process) temperature. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF2 ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Journal of the Korean Vacuum Society
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• v.2 no.4
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• pp.468-473
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• 1993

Damages on Si substrate induced by Ar ion implantation and it annealing behavior during rapid thermal annealing were investigated by the cross-sectional TEM (transmissin electron microscopy), RB(Rutherfordbackscattering) spectra an dthermal wave (TW) modulation reflectance methods. Continuous amorphous layer extending to the surface were generated by Ar ion implantation for higher doses than 1 $\times$1015cm-2. The recrystallization of the amorphous layer prodeeded as the annealing temperature increased . However the amorphous /crystal interfacial undulations caused the micro twins and damage clusters. Damage clusters generated by lower doses than 1 $\times$1015 cm-2 disappeared slowly as the annealing temperature increased, but even at 110$0^{\circ}C$ a few damage clusters still remained.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.51-58
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• 1993

N-channel TFTs fabricated on the pre-amorphized (by Si ion implantation) and recrystallized Si film having 10.1V threshold voltage, 20.7cm$^{2}$/V$\cdot$s field effect mobility and ~10$^{5}$/ ON/OFF ratio, whowed improved characteristics comparing to those obtained from the as-deposited (by LPCVD) poly Si film which had 11.2V, 9cm$^{2}$/V$\cdot$s and ~10$^{4}$ respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.90-90
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• 2010

We investigated the modification of optical response properties of titanium dioxide (TiO2) coatings on the ceramic water-purification filters by using ultraviolet-visible absorption spectroscopy and X-ray diffraction. The TiO2 coatings were prepared on ceramic substrate by e-beam evaporation method. These amorphous TiO2 were turned into anatase phase by heat treatment at $700^{\circ}C$ for 2 hours. The doping of N atoms into the TiO2 coatings was done by using 70KeV of N＋ ion implantation with the dose of $1.0{\times}1017$ ions/cm2, followed by post-irradiation heat treatment at $550^{\circ}C$ for 2 hours. Methylene blue test of TiO2 coatings to solar irradiation showed that the post-evaporation heated TiO2 was photocatalytic and N-doped TiO2 reacted to the visible part of solar irradiation.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.212-222
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• 1992

To use polycrystalline Si Thin Film Transistor (poly-Si TFT) in high density SRAM instead of High Load Resistor (HLR), TFT is needed to show good electrical characteristics such as large carrier mobility, low leakage current, high driver current and low subthreshold swing. To satisfy these electrical characteristics, the trap state density must be reduced in the channel poly. Technological issues pertinent to the channel poly fabrication process are investigated and discussed. They are solid phase growth (SPG), Si-ion implantation, laser annealing and hydrogenation. The electrical properties of several CVD oxides used as the gate oxide of TFT are compared. The dependence of the electrical characteristics of TFT on source-drain ion-implantation dose, drain offset length and dopant lateral diffusion are also described.

• Proceedings of the KIEE Conference
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• 1998.07e
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• pp.1797-1799
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• 1998

Plasma source ion implantation(PSII) is a non-line-of-sight technique for surface modification of materials which is effective for non-planar targets. A apparatus of 30kV PSII is established and plasma characteristics are diagnosed by using a Langmuir probe. A spherical target is immersed in argon plasma and biased negatively by a series of high voltage pulses. Sheath evolution is measured by using a Langmuir probe and compared with the result of computer simulations.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1546-1548
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• 1997

We investigated microhardness, friction, wear and wettability of polyimide for finding out the influence of ion implantation on surface properties. For increasing doses microhardness increased. A reduction of the friction coefficient was most cases correlated with a reduction of wear. The contact angles of water for $B^+$, $N^+$ implanted polyimide decreased from $76^{\circ}$ to zero, as the fluences increased energy of 50, 200 keV.