• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.375-381
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• 2001

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide bit-line with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance tungsten bit-line fabrication process with various RTP(Rapid Thermal Process) temperature and additional ion implantation. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF$_2$ ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Transactions of Materials Processing
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• v.14 no.5 s.77
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• pp.473-476
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• 2005

The demand of on-chip total analyzing system with MEMS (micro electro mechanical system) bio/chemical sensor is rapidly increasing. In on-chip total analyzing system, to detect the bio/chemical products with submicron feature size, a filtration system with nano-filter is required. One of the conventional methods to fabricate nano-filter is to use direct patterning or RIE (reactive ion etching). However, those procedures are very costly and are not suitable fur mass production. In this study, we suggested new fabrication method for a nano-filter based on replication process, which is simple and low cost process. After the Si master was fabricated by laser interference lithography and reactive ion etching process, the polymeric mold was replicated by UV-imprint process. Metallic nano-filter was fabricated after removing the polymeric part of metal deposited polymeric mold. Finally, our fabrication method was applied to metallic nano-filter with $1{\mu}m$ pitch size and $0.4{\mu}m$ hole size for bacteria sensor application.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.275-277
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• 2005

In a lithium-ion battery which is being used in many portable electronic goods, electrolyte is disaggregated and then the gas is happened when electric charging volt is over the 4.5V. So, the pressure on the safety valve is increased and electrolyte is leaked out in the cell. It leads to the risk of explosion. On the other hand, in the case which the battery is discharged excessively, the negative pole is damaged and the performance of the battery is deteriorated. The protection module of a lithium-ion battery is used for preventing such risk and the inspection system is needed to check the performance of such protection module. In this research, a PC-based auto inspection system is developed for the inspection of a battery protection module using Dallas chipset. In the inspection system, AVRl28 chip is used as a controller and the communication protocol is developed for the data communication between the protection module and the AVR128 chip. And GPIB interface is used for the control of measuring devices. Also, MMI environment is developed using LabView for convenient monitoring by the tester.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.485-496
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• 2008

As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1551_1552
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• 2009

In this paper, we presented the packaging technologies of CMOS ISFET(Ion Sensitive Field Effect Transistor) pH sensor using post-CMOS process and MCP(Multi Chip Packaging). We have proposed and developed two types of packaging technology. one is one chip, which sensing layer is deposited on the gate metal of standard CMOS ISFET, the other is two chip type, which sensing layer is separated from CMOS ISFET and connected by bonding wire. These proposed packaging technologies would make it easy to fabricate CMOS ISFET pH sensor and to make variety types of pH sensor.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.5
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• pp.1-10
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• 1998

A GaAs MMIC composed of VCO (voltage controlled oscillator) and mixer for PCS receiver has been developed using 1.mu.m ion implanted GaAs MESFET process. The VCO consists of a colpitts-type oscillator with a dielectric resonator and the circuit configuration of the mixer is a dual-gate type with an asymmetric combination of LO and RF FETs for the improvement of intermodulation characteristics. The common-source self-biasing is used in all circuits including a buffer amplifier and mixer, achieving a single power supply (3V) operation. The total power dissipation is 78mW. The VCO chip shows a phase noise of-99 dBc/Hz at 100KHz offset. The combined VCO/mixer chip shows a flat conversion gain of 2dB, the frequency-tuning factor of 80MHz/volts in the varacter bias ranging from 0.5V to 0.5V , and output IP3 of dBm at varactor bias of 0V. The fabricated chip size is 2.5mm X 1.4mm.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.579-581
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• 2004

We wish to develop micro-total analysis system (TAS) on a chip, and to make a trial approach to solve the important problem that is to detect ions separated by the electric field. We propose an idea, which is as for rotational motions of dipolar ions, which are affected by the ion atmosphere in outer regions. This is a new kind of the ion-sensitive field effect transistor (ISFET). We wish to develop the ISFET chips, and give more effective, fast and sensitive, capillary electrophoresis is designed in near future.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.76-76
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• 2012

Surface engineering of polymers has a broad array of scientific and technological applications that range from tissue engineering, regenerative medicine, microfluidics and novel lab on chip devices to building mechanical memories, stretchable electronics, and devising tunable surface adhesion for robotics. Recent advancements in the field of nanotechnology have provided robust techniques for controlled surface modification of polymers and creation of structural features on the polymeric surface at submicron scale. We have recently demonstrated techniques for controlled surfaces of soft and relatively hard polymers using ion beam irradiation and plasma treatment, which allows the fabrication of nanoscale surface features such as wrinkles, ripples, holes, and hairs with respect to its polymers. In this talk, we discuss the underlying mechanisms of formation of these structural features. This includes the change in the chemical composition of the surface layer of the polymers due to ion beam irradiation or plasma treatment and the instability and mechanics of the skin-substrate system. Using ion beam or plasma irradiation on polymers, we introduce a simple method for fabrication of one-dimensional, two-dimensional and nested hierarchical structural patterns on polymeric surfaces on various polymers such as polypropylene (PP), polyethylene (PE), poly (methyl methacrylate) PMMA, and polydimethylsiloxane (PDMS).

• Korean Journal of Materials Research
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• v.17 no.10
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• pp.509-515
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• 2007

In order to fabricate adhesiveless 2-layer flexible copper clad laminate (FCCL) used for COF (chip on film) with high peel strength, polyimide (PI; Kapton-EN, $38\;{\mu}m$) surface was modified by reactive $O_2^+$ and $N_2O^+$ ion beam irradiation. 300 mm-long linear electron-Hall drift ion source was used for ion irradiation with ion current density (J) higher than $0.5\;mA/cm^2$ and energy lower than 200 eV. By vacuum web coating process, PI surface was modified by linear ion source and then 10-20 nm thick Ni-Cr and 200 nm thick Cu film were in-situ sputtered as a tie layer and seed layer, respectively. Above this sputtered layer, another $8-9{\mu}m$ thick Cu layer was grown by electroplating and subsequently acid and base resistance and thermal stability were tested for examining the change of peel strength. Peel strength for the FCCLs treated by both $O_2^+$ and $N_2O^+$ ion irradiation showed similar magnitudes and increased as the thickness of tie layer increased. FCCL with Cu (200 nm)/Ni-Cr (20 nm)/PI structure irradiated with $N_2O^+$ at $1{\times}10^{16}/cm^2$ ion fluence was proved to have a strong peel strength of 0.73 kgf/cm for as-received and 0.34 kgf/cm after thermal test.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.