• Journal of the Korean Society for Precision Engineering
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• v.21 no.6
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• pp.153-159
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• 2004

In this study, a new process to pattern directly on a thin metal layer using improved nano replication printing (nRP) process is suggested to evaluate the possibilities of fabricating a stamp for nano-imprinting. In the nRP process, any figure can be replicated from a bitmap figure file in the range of several micrometers with nano-scaled details. In the process, liquid-state resins are polymerized by two-photon absorption which is induced by femto-second laser. A thin gold layer was sputtered on a glass plate and then, designed patterns or figures were developed on the gold layer by newly developed top-down building approach. Generally, stamps fur nano-imprinting have been fabricated by using the costly electron-beam lithography process combined with a reactive ion-etching process. Through this study, the effectiveness of the improved nRP process is evaluated to make a stamp with the resolution of around 200nm with reduced cost.

• Journal of the Korean institute of surface engineering
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• v.45 no.4
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• pp.151-154
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• 2012

A hydrophobic surface has been fabricated on aluminum by two-step surface treatment processes consisting of structure modification and surface coating. Nature inspired micro nano scale structures were artificially created on the aluminum surface by a blasting and Ar ion beam etching. And a hydrophobic thin film was coated by a trimethylsilane ($(CH_3)_3SiH$) plasma deposition to minimize the surface energy of the micro nano structure surface. The contact angle of micro nano structured aluminum surface with the trimethylsilane coating was $123^{\circ}$ (surface energy: 9.05 $mJ/m^2$), but the contact angle of only trimethylsilane coated sample without the micro nano surface structure was $92^{\circ}$ (surface energy: 99.15 $mJ/m^2$). In the hydrophobic treatment of aluminum surface, a trimethylsilane coated sample having the micro nano structure was more effective than only trimethylsilane coated sample without the micro nano structure.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.287-287
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• 2011

ITRS(international technology roadmap for semiconductors)에 따르면 MOS (metal-oxide-semiconductor)의 CD(critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/SiO2를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두되고 있다. 일반적으로 metal gate를 식각시 정확한 CD를 형성시키기 위해서 plasma를 이용한 RIE(reactive ion etching)를 사용하고 있지만 PIDs(plasma induced damages)의 하나인 PICD(plasma induced charging damage)의 발생이 문제가 되고 있다. PICD의 원인으로 plasma의 non-uniform으로 locally imbalanced한 ion과 electron이 PICC(plasma induced charging current)를 gate oxide에 발생시켜 gate oxide의 interface에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 metal gate의 식각공정에 HDP(high density plasma)의 ICP(inductively coupled plasma) source를 이용한 중성빔 시스템을 사용하여 PICD를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. 식각공정조건으로 gas는 HBr 12 sccm (80%)와 Cl2 3 sccm (20%)와 power는 300 w를 사용하였고 200 eV의 에너지로 식각공정시 TEM(transmission electron microscopy)으로 TiN의 anisotropic한 형상을 볼 수 있었고 100 eV 이하의 에너지로 식각공정시 하부층인 HfO2와 높은 etch selectivity로 etch stop을 시킬 수 있었다. 실제 공정을 MOS의 metal gate에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU(North Carolina State University) CVC model로 effective electric field electron mobility를 구한 결과 electorn mobility의 증가를 볼 수 있었고 또한 mos parameter인 transconductance (Gm)의 증가를 볼 수 있었다. 그 원인으로 CP(Charge pumping) 1MHz로 gate oxide의 inteface의 분석 결과 이러한 결과가 gate oxide의 interface trap양의 감소로 개선으로 기인함을 확인할 수 있었다.

• Current Optics and Photonics
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• v.2 no.2
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• pp.125-133
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• 2018

We report an in-depth analysis of the design and fabrication of multilayer dielectric (MLD) diffraction gratings for spectral beam combining at a wavelength of 1055 nm. The design involves a near-Littrow grating and a modal analysis for high diffraction efficiency. A range of wavelengths, grating periods, and angles of incidence were examined for the near-Littrow grating, for the $0^{th}$ and $-1^{st}$ diffraction orders only. A modal method was then used to investigate the effect of the duty cycle on the effective indices of the grating modes, and the depth of the grating was determined for only the $-1^{st}$-order diffraction. The design parameters of the grating and the matching layer thickness between grating and MLD reflector were refined for high diffraction efficiency, using the finite-difference time-domain (FDTD) method. A high reflector was deposited by electron-beam evaporation, and a grating structure was fabricated by photolithography and reactive-ion etching. The diffraction efficiency and laser-induced damage threshold of the fabricated MLD diffraction gratings were measured, and the diffraction efficiency was compared with the design's value.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.2 s.43
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• pp.17-21
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• 2007

Dense and periodic arrays of holes and Si nano dots were fabricated on silicon substrate. The nanopatterned holes were approximately $15{\sim}40nm$ wide, 40 nm deep and $40{\sim}80\;nm$ apart. To obtain nano-size patterns, self?assembling diblock copolymer were used to produce layer of hexagonaly ordered parallel cylinders of polymethylmethacrylate (PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS. $100\;{\AA}-thick$ Au thin film was deposited by using e-beam evaporator. PS template was removed by lift-off process. Arrays of Au nano dots were transferred by using Fluorine-based reactive ion etching(RE). Au nano dots were removed by sulfuric acid. Si nano dots size and height were $30{\sim}70\;nm$ and $10{\sim}20\;nm$ respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.223-223
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• 2012

Surface engineering plays a significant role in fabricating highly functionalized materials applicable to industrial and biomedical fields. Surface wrinkles and folds formed by ion beam or plasma treatment are buckling-induced patterns and controlled formation of those patterns has recently gained considerable attention as a way of creating well-defined surface topographies for a wide range of applications. Surface wrinkles and folds can be observed when a stiff thin layer attached to a compliant substrate undergoes compression and plasma treatment is one of the techniques that can form stiff thin layers on compliant polymeric substrates, such as poly (dimethylsiloxane) (PDMS). Here, we report two effective methods using plasma modification techniques for controlling the formation of surface wrinkles and folds on flat or patterned PDMS substrates. First, we show a method of creating wrinkled diamond-like carbon (DLC) film on grooved PDMS substrates. Grooved PDMS substrates fabricated by a molding method using a grooved master prepared by photolithography and a dry etching process were treated with argon plasma and subsequently coated with DLC film, which resulted in the formation of wrinkled DLC film aligning perpendicular to the steps of the pre-patterned ridges. The wavelength and the amplitude of the wrinkled DLC film exhibited variation in the submicron- to micron-scale range according to the duration of argon plasma pre-treatment. Second, we present a method for controlled formation of folds on flat PDMS substrates treated with oxygen plasma under large compressive strains. Flat PDMS substrates were strained uniaxially and then treated with oxygen plasma, resulting in the formation of surface wrinkles at smaller strain levels, which evolved into surface folds at larger strain levels. Our results demonstrate that we can control the formation and evolution of surface folds simply by controlling the pre-strain applied to the substrates and/or the duration of oxygen plasma treatment.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.393-393
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• 2012

Optically active nanostructures such as subwavelength moth-eye antireflective structures or surface enhanced Raman spectroscopy (SERS) active structures have been demonstrated to provide the effective suppression of unwanted reflections as in subwavelength structure (SWS) or effective enhancement of selective signals as in SERS. While various nanopatterning techniques such as photolithography, electron-beam lithography, wafer level nanoimprinting lithography, and interference lithography can be employed to fabricate these nanostructures, roll-to-roll (R2R) nanoimprinting is gaining interests due to its low cost, continuous, and scalable process. R2R nanoimprinting requires a master to produce a stamp that can be wrapped around a quartz roller for repeated nanoimprinting process. Among many possibilities, two different types of mask can be employed to fabricate optically active nanostructures. One is self-assembled Au nanoparticles on Si substrate by depositing Au film with sputtering followed by annealing process. The other is monolayer silica particles dissolved in ethanol spread on the wafer by spin-coating method. The process is optimized by considering the density of Au and silica nano particles, depth and shape of the patterns. The depth of the pattern can be controlled with dry etch process using reactive ion etching (RIE) with the mixture of SF6 and CHF3. The resultant nanostructures are characterized for their reflectance using UV-Vis-NIR spectrophotometer (Agilent technology, Cary 5000) and for surface morphology using scanning electron microscope (SEM, JEOL JSM-7100F). Once optimized, these optically active nanostructures can be used to replicate with roll-to-roll process or soft lithography for various applications including displays, solar cells, and biosensors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.4
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• pp.259-267
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• 2002

We present a novel 3D fabrication method with single X-ray process utilizing an X-ray mask in which a micro-actuator is integrated. An X-ray absorber is electroplated on the shuttle mass driven by the integrated micro-actuator during deep X-ray exposures. 3D microstructures are revealed by development kinetics and modulated in-depth dose distribution in resist, usually PMMA. Fabrication of X-ray masks with integrated electrothermal xy-stage and electrostatic actuator is presented along with discussions on PMMA development characteristics. Both devices use $20-\mu\textrm{m}$-thick overhanging single crystal Si as a structural material and fabricated using deep reactive ion etching of silicon-on-insulator wafer, phosphorous diffusion, gold electroplating, and bulk micromachining process. In electrostatic devices, $10-\mu\textrm{m}-thick$ gold absorber on $1mm{\times}1mm$ Si shuttle mass is supported by $10-\mu\textrm{m}-wide$, 1-mm-long suspension beams and oscillated by comb electrodes during X-ray exposures. In electrothermal devices, gold absorber on 1.42 mm diameter shuttle mass is oscillated in x and y directions sequentially by thermal expansion caused by joule heating of the corresponding bent beam actuators. The fundamental frequency and amplitude of the electrostatic devices are around 3.6 kHz and $20\mu\textrm{m}$, respectively, for a dc bias of 100 V and an ac bias of 20 VP-P (peak-peak). Displacements in x and y directions of the electrothermal devices are both around $20{\;}\mu\textrm{m}$at 742 mW input power. S-shaped and conical shaped PMMA microstructures are demonstrated through X-ray experiments with the fabricated devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.