• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.436-437
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• 2012

Double patterning technology (DPT) has been suggested as a promising candidates of the next generation lithography technology in FLASH and DRAM manufacturing in sub-40nm technology node. DPT enables to overcome the physical limitation of optical lithography, and it is expected to be continued as long as e-beam lithography takes place in manufacturing. Several different processes for DPT are currently available in practice, and they are litho-litho-etch (LLE), litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP) [1]. The self-aligned approach is regarded as more suitable for mass production, but it requires precise control of sidewall space etch profile for the exact definition of hard mask layer. In this paper, we propose etch end point detection (EPD) in spacer etching to precisely control sidewall profile in SADP. Conventional etch EPD notify the end point after or on-set of a layer being etched is removed, but the EPD in spacer etch should land-off exactly after surface removal while the spacer is still remained. Precise control of real-time in-situ EPD may help to control the size of spacer to realize desired pattern geometry. To demonstrate the capability of spacer-etch EPD, we fabricated metal line structure on silicon dioxide layer and spacer deposition layer with silicon nitride. While blanket etch of the spacer layer takes place in inductively coupled plasma-reactive ion etching (ICP-RIE), in-situ monitoring of plasma chemistry is performed using optical emission spectroscopy (OES), and the acquired data is stored in a local computer. Through offline analysis of the acquired OES data with respect to etch gas and by-product chemistry, a representative EPD time traces signal is derived. We found that the SE-EPD is useful for precise control of spacer etching in DPT, and we are continuously developing real-time SE-EPD methodology employing cumulative sum (CUSUM) control chart [2].

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.658-658
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• 2013

Graphene is an attractive material for various device applications due to great electrical properties and chemical properties. However, lack of band gap is significant hurdle of graphene for future electrical device applications. In the past few years, several methods have been attempted to open and tune a band gap of graphene. For example, researchers try to fabricate graphene nanoribbon (GNR) using various templates or unzip the carbon nanotubes itself. However, these methods generate small driving currents or transconductances because of the large amount of scattering source at edge of GNRs. At 2009, Bai et al. introduced graphene nanomesh (GNM) structures which can open the band gap of large area graphene at room temperature with high current. However, this method is complex and only small area is possible. For practical applications, it needs more simple and large scale process. Herein, we introduce a photosensitive graphene device fabrication using CdSe QD coated nano-porous graphene (NPG). In our experiment, NPG was fabricated by thin film anodic aluminum oxide (AAO) film as an etching mask. First of all, we transfer the AAO on the graphene. And then, we etch the graphene using O2 reactive ion etching (RIE). Finally, we fabricate graphene device thorough photolithography process. We can control the length of NPG neckwidth from AAO pore widening time and RIE etching time. And we can increase size of NPG as large as 2 $cm^2$. Thin CdSe QD layer was deposited by spin coatingprocess. We carried out NPG structure by using field emission scanning electron microscopy (FE-SEM). And device measurements were done by Keithley 4200 SCS with 532 nm laser beam (5 mW) irradiation.

• Applied Chemistry for Engineering
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• v.10 no.3
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• pp.343-348
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• 1999

The iron silicide films were prepared by chemical vapor deposition method using rf-plasma in variations of substrate temperature. rf-power, and ratio of $SiH_4$ and Fe-precursor. While iron silicide films are generally grown by ion beam synthesis (IBS) method of multi-step process, it is confirmed that iron silicide or $\beta$-phase consolidated $Fe_aSi_bC_cH_d$ was formed by one-step process in this study. The characteristics of films is variable because the different amounts of carbon and hydrogen was involved in the films as a function of dilute ratio of Fe-precursors and silane. It was shown that the different characteristics of films in carbon and hydrogen following the ratio of Fe-precursor and silane. The optical gap energy of films fabricated according to substrate temperature was invariant because active site brought in desorption of hydrogen was limiled. When rf-power was above 240 watt, the optical gap energy turned out to have high values because of dangling bonds increased by etching.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.463-463
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• 2012

ITRS (international technology roadmap for semiconductors)에 따르면 MOS(metal-oxide-semiconductor)의 CD (critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/$SiO_2$를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두된다고 보고하고 있다. 일반적으로 high-k dielectric를 식각시 anisotropic 한 식각 형상을 형성시키기 위해서 plasma를 이용한 RIE (reactive ion etching)를 사용하고 있지만 PIDs (plasma induced damages)의 하나인 PIED (plasma induced edge damage)의 발생이 문제가 되고 있다. PIED의 원인으로 plasma의 direct interaction을 발생시켜 gate oxide의 edge에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 high-k dielectric의 식각공정에 HDP (high density plasma)의 ICP (inductively coupled plasma) source를 이용한 원자층 식각 장비를 사용하여 PIED를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. One-monolayer 식각을 위한 1 cycle의 원자층 식각은 총 4 steps으로 구성 되어 있다. 첫 번째 step은 Langmuir isotherm에 의하여 표면에 highly reactant atoms이나 molecules을 chemically adsorption을 시킨다. 두 번째 step은 purge 시킨다. 세 번째 step은 ion source를 이용하여 발생시킨 Ar low energetic beam으로 표면에 chemically adsorbed compounds를 desorption 시킨다. 네 번째 step은 purge 시킨다. 결과적으로 self limited 한 식각이 이루어짐을 볼 수 있었다. 실제 공정을 MOS의 high-k dielectric에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU (North Carolina State University) CVC model로 구한 EOT (equivalent oxide thickness)는 변화가 없으면서 mos parameter인 Ion/Ioff ratio의 증가를 볼 수 있었다. 그 원인으로 XPS (X-ray photoelectron spectroscopy)로 gate oxide의 atomic percentage의 분석 결과 식각 중 발생하는 gate oxide의 edge에 trap의 감소로 기인함을 확인할 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.382-382
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• 2012

Nanostructures have a larger surface/volume ratio as well as unique mechanical, physical, chemical properties compared to existing bulk materials. Materials for biomedical implants require a good biocompatibility to provide a rapid recovery following surgical procedure and a stabilization of the region where the implants have been inserted. The biocompatibility is evaluated by the degree of the interaction between the implant materials and the cells around the implants. Recent researches on this topic focus on utilizing the characteristics of the nanostructures to improve the biocompatibility. Several studies suggest that the degree of the interaction is varied by the relative size of the nanostructures and cells, and the morphology of the surface of the implant [1, 2]. In this paper, we fabricate the nanowires on the Ti substrate for better biocompatible implants and other biomedical applications such as artificial internal organ, tissue engineered biomaterials, or implantable nano-medical devices. Nanowires are fabricated with two methods: first, nanowire arrays are patterned on the surface using e-beam lithography. Then, the nanowires are further defined with deep reactive ion etching (RIE). The other method is self-assembly based on vapor-liquid-solid (VLS) mechanism using Sn as metal-catalyst. Sn nanoparticle solutions are used in various concentrations to fabricate the nanowires with different pitches. Fabricated nanowries are characterized using scanning electron microscopy (SEM), x-ray diffraction (XRD), and high resolution transmission electron microscopy (TEM). Tthe biocompatibility of the nanowires will further be investigated.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.11
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• pp.85-90
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• 1998

A 1 4 polymeric optical power divider based on the multimode interference effect is designed and fabricated. The two dimensional finite difference beam propagation method has been utilized in designing the device. Polymers used for the core layer and the cladding layer are Cyclotene-3022 and UV-15, respectively. The device is fabricated by the reactive ion etching method. The splitting ratio of the fabricated device is 0.93 : 1.00 : 0.93 : 0.90 for TE mode and 0.84 : 0.94 : 1.00 : 0.83 for TM mode. The advantages of this device are small size and low polarization-dependence.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.424-424
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• 2009

그라핀은 밴드갭이 없어서 세미메탈의 성질을 띠므로 초고속 RF 소자에는 응용이 가능하지만, 현재 사용되는 반도체 칩에 사용하기가 불가능하다. 그러나 그라핀을 매우 좁은 리본 형태로 만들 경우 밴드갭이 생기고 이에 따라 반도체특성을 뛰게 된다. 이러한 특성은 시뮬레이션을 통해서만 이해되다가 2007년 P. Kim이 그라핀 나노리본의 밴드캡이 리본의 폭이 좁아짐에 따라 증가함을 실험적으로 최초로 발표하였다. 하지만 그라핀을 나노리본형태로 식각 방법에 대해서는 정확히 연구되지 않았다. 따라서 본 연구에서는 $O_2$ plasma ashing 방법을 이용하여 그라핀을 식각하는 방법에 대해 연구하였다. 먼저 Si기판을 initial cleaning 한 후, highly-oriented pyrolytic graphite(HOPG)를 이용하여 기존의 mechanical exfoliation 방식을 통해 그라핀을 형성하였다. Photo-lithography 방법을 통하여 패터닝한 후, 그라핀을 식각하기 위하여 Reactive Ion Etcher (RIE) system을 이용한 $O_2$ plasma ashing을 50 W에서 1 분간 실시하였다. 다시 image reverse photo-lithography 과정과 E-beam evaporator system를 통해서 Al 전극을 형성하여 graphene-FET를 제작하였고, 광학 현미경과 AFM (Atomic force microscope)을 통해 두께를 확인하였다. 본 연구를 통하여 $O_2$ plasma ashing을 이용하여 쉽게 그라 E을 식각할 수 있음을 확인 하였으며, 제작된 소자의 전기적 특성에 대해서 현재 실험중에 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.101-105
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• 2006

Nanoscale floating-gate characteristic of colloidal Au nanoparticles electrostatically assembled on the oxidized surface of Si nanowires have been investigated. The Si nanowire split-gate transistor structure was fabricated by electron beam lithography and subsequent reactive ion etching. Colloidal Au nanoparticles with ${\sim}5$ nm diameters were selectively deposited onto the Si nanowire surface by 2 min electrophoresis. It was found that electric fields applied to the self-aligned split side gates allowed charge to be transferred on the Au nanoparticles. It was observed that the depletion mode cutoff voltage, induced by the self-aligned side gates, was shifted by more than 1 V after Au nanoparticle electrophoresis. This may be due to the semi-one dimensional nature of the narrow Si nanowire transport channel, having much enhanced sensitivity to charges on the surface.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.244.2-244.2
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• 2014

금속, 플라스틱, 유리 등의 재료 표면에 다양한 색상을 표현하기 위해 일반적으로 습식 도금을 많이 적용하고 있다. 하지만 습식 도금은 공정 수가 많을 뿐만 아니라 위험물질 및 오염물질을 많이 사용하기 때문에 산업사고, 환경오염 등을 야기 시킨다. 따라서 본 연구에서는 친환경적 방법인 물리적기상증착(PVD ; Physical Vapor Deposition) 방식의 한 종류인 스퍼터링(Sputtering)으로 색상을 구현하였다. PVD 방식의 증착은 습식 도금 방식에 비해 친환경적이며, 전처리에서 후처리까지 한 공정으로 가능하다는 점이다. 스퍼터링은 PVD의 다른 방식인 E-beam 방식에 비해 대량생산을 할 수 있다는 장점이 있다. 양산형 스퍼터링 장비(${\Phi}1200mm{\times}H1400mm$)로 실험을 진행하였으며, 증착 물질은 Ti, Al, Cr 을 사용하였고, 반응성 가스(Reactive Gas) 로는 N2, C2H2 가스를 사용하였다. 전처리는 LIS (Linear Ion Source)로 식각(Etching) 하였고, 펄스직류전원공급장치(Pulsed DC Power Supply)를 사용하여 증착 하였으며, 증착시 기판에 bias (-100 V)를 인가 하였다. 그 결과 회색계열, 갈색계열 등 여러가지 색을 구현할 수 있었으며, 증착된 박막의 특성을 알아보기 위하여 색차계, 내마모 시험기, 연필경도 시험기를 사용하였다. 향후 후처리 공정으로 내지문(AF ; anti fingerprint coating) 박막 등과 같은 실용적인 박막을 증착할 계획이다.

• Korean Journal of Materials Research
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• v.14 no.6
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• pp.413-419
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• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).