• The Journal of Internal Korean Medicine
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• v.24 no.4_2
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• pp.1037-1045
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• 2003

Objectives: Dementia is a kind of chronic, progressive, degenerative disease. The symptoms results in troubles in intellectual functions. memory, orientation, intelligence, judgement, common sense and calculating ability. The Korean version of Mini-Mental State Examination(MMSE-K) has been used widely to screen cognitive impairment of the elderly in Korea. This instrument has been specifically developed and evaluated for the assessment of cognitive function in older Korean populations. Methods: Cognitive function was evaluated by the Korean version of Mini-Mental State Examination(MMSE-K). This patient was diagnosed as Vascular dementia and We treated her cognitive impairment with Gagambosim-tang(Jiajianbuxin-tang). Results: After treated with Gagambosim-tang(Jiajianbuxin-tang), Cognitive function was improved. Conclusion: This report may have a meaning to treat Vascular dementia.

• The KIPS Transactions:PartA
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• v.8A no.3
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• pp.189-200
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• 2001

This paper proposes a memory allocation model for Real-Time Linux. The proposed model allows users to create several continuous memory regions in an application, to specify an appropriate region allocation policy for each memory region, and to request memory blocks from a necessary memory region. Instead of using single memory management module in order to support the proposed model, we adopt two-layered structure that is consisted of region allocators implementing allocation policies and a region manager controlling regions and region allocator modules. This structure separates allocation policy from allocation mechanism, thus allows system developers to implement same allocation policy using different algorithms in case of need. IN addition, it enables them to implement new allocation policy using different algorithms in case of need. In addition, it enables them to implement new allocation policy easily as long as they preserver predefined internal interfaces, to add the implemented policy into the system, and to remove unnecessary allocation policies from the system, Because the proposed model provides various allocation policies implemented previously, system builders can also reconfigure the system by just selecting most appropriate policies for a specific application without implementing these policies from scratch.

• The KIPS Transactions:PartD
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• v.18D no.3
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• pp.157-168
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• 2011

Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1016-1021
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• 2003

The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.257-258
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• 2006

In this paper, we address several issues in the real time implementation of MPEG-1 Layer II decoder on a fixed-point digital signal processor (DSP), especially TMS320C6416. There is a trade-off between processing speed and the size of program/data memory for the optimal implementation. In a view of the speed optimization, we first convert the floating point operations into fixed point ones with little degradation in audio quality, and then the look-up tables used for the inverse quantization of the audio codec are forced to be located into the internal memory of the DSP. And then, window functions and filter coefficients in the decoder are precalculated and stored as constant, which makes the decoder faster even larger memory size is required. It is shown from the real-time experiments that the fixed-point implementation enables us to make the decoder with a sampling rate of 48 kHz operate with 3 times faster than real-time on TMS320C6416 at a clock rate of 600 MHz.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.641-644
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• 2003

본 논문은 RTOS(Real-Time Operation System, 리턴어드레스를 위한 유저스택사용 RTOS가 탑재된 CE(Consumer Electronic)제품상에서 리턴어드레스가 유저스택으로 저장하는 것을 지원하지 않는 컴파일러를 위한 알고리즘이며 실험을 위하여 제안된 알고리즘을 상용 컴파일러에 적용하여 비교해보도록 하겠다. 우선 기존 컴파일러 알고리즘으로는 Task마다 할당된 유저스택영역이 존재하며 Task가 수행중 발생된 리턴어드레스는 즉시 할당된 유저스택으로 저장하는 알고리즘을 갖고있다. 이런 알고리즘으로 인하여 인스트럭션이 수행중 빈번한 메모리 접근(external memory)가 발생한다. 그러나 제안된 알고리즘은 Task 수행중에는 리턴어드레스를 시스템스택(internal memory)에 저장한 후 Task 전환이 발생할 경우 일시에 시스템 스택에 저장된 리턴어드레스를 유저스택으로 이동하게 되므로 Task 수행중에는 시스템 스택만을 접근하므로 task의 수행시간을 단축할 수가 있다. 그리고 실험을 위하여 상용 컴파일러들에 본 알고리즘을 적용하였다. 상용 컴파일러로는 매번 리턴어드레스를 자동으로 Task별 할당된 유저스택에 저장할 수 있도록 지원해주는 TASKING 컴파일러(Altium 사)와 그렇지 않은 KEIL컴파일러(KEIL사)가 있으며 본 알고리즘을 KEIL 컴파일러에 적용하여 실험을 하여 TASKING 컴파일러와 비교한 결과 유저스택을 지원하는 TASKING(Altium사) 컴파일러에서 구현한 CE제품의 Response time이 KEIL 컴파일러에서 구현한 CE제품의 Response time 값이 같게 나왔다. 그러므로 KEIL 컴파일러상에 본 알고리즘을 적용시킬 경우 RTOS가 탑재된 CE제품을 보다 용이하게 구현할 수가 있다.

• Smart Structures and Systems
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• v.30 no.3
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• pp.245-253
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• 2022

A two-layer beam consisting of an elastoplastic layer and a functional layer made of shape memory alloy (SMA) TiNi is considered. Constitutive relations for SMA are set by a microstructural model capable to calculate strain increment produced by arbitrary increments of stress and temperature. This model exploits the approximation of small strains. The equations to calculate the variations of the strain and the internal variables are based on the experimentally registered temperature kinetics of the martensitic transformations with an account of the crystallographic features of the transformation and the laws of equilibrium thermodynamics. Stress and phase distributions over the beam height are calculated by steps, by solving on each step the boundary-value problem for given increments of the bending moment (or curvature) and the tensile force (or relative elongation). Simplifying Bernoulli's hypotheses are applied. The temperature is considered homogeneous. The first stage of the numerical experiment is modeling of preliminary deformation of the beam by bending or stretching at a temperature corresponding to the martensitic state of the SMA layer. The second stage simulates heating and subsequent cooling across the temperature interval of the martensitic transformation. The curvature variation depends both on the total thickness of the beam and on the ratio of the layer's thicknesses.

• The Journal of Internal Korean Medicine
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• v.40 no.5
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• pp.920-928
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• 2019

Objectives: After epidural hemorrhage, sequelae may cause cognitive impairments, such as attention, memory, and performance disturbances. This case study reports on the use of traditional Korean medicine in a patient with cognitive impairments after a traumatic epidural hemorrhage. Methods: During the 46-day hospitalization period, traditional Korean medicine treatments, including Sunkihwalhyul-tang-gamibang, Ukgan-san-gajinpibanha Granule, Kyungohk-go, acupuncture, and cupping, were administered. The degree of cognitive impairment was measured based on the Mini Mental State Examination-Korea (MMSE-K), Modified Barthel Index (MBI), and correct answer ratio. Results: After traditional Korean medicine treatment, the MMSE-K score increased from 13 to 19 and the MBI score increased from 63 to 71. The patient's conversations in daily life also proceeded more smoothly than before hospitalization, and the correct answer ratio rose. Conclusion: This case reports the improvement of cognitive impairment after traumatic epidural hemorrhage in response to traditional Korean medicine treatment; further study is needed.

• Journal of KSNVE
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• v.6 no.2
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• pp.205-214
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• 1996

Active noise control(ANC) requires the full capability of a modern digital signal processing module. This paper describes the digital signal processing unit which is designed for ANC of noise fields in passenger car. System hardware is designed to allow software controlled versatility as well as fully qutomatic operation. The developed system is provided with the ability to be self-operated except the case of upload/download of data and program between the personal computer and the system memory. Experimental results are presented to demonstrate ANC performance of noise fields in lightly damped enclosure and passenger car.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.152-161
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• 1996

This paper descrisbes the implementation of a 20D DCT that can be used for video conference, JPEG, and MPEG-related applications. The implemented DCT consists of two 1-D DCTs and a transposed memory between them, and uses ROM-based multipliers instead of conventional ones. As the system bit length, the minimum bit length that satisfies the accuracy specified by the ITU standard H.261 was chosen through the simulations using the C language. The proposed design uses a dual port RAM for the transposed memory, and processes two bits of input-pixel data simultaneously t ospeed up addition process using two sets of ROMs. The basic system architecture was designed using th Synopsys schematic editor, and internal modules were described in VHDL and synthesized to logic level after simulation. Then, the compass silicon compiler was used to create the final lyout with 0.8um CMOS libraries, using the standard cell approach. The final layout contains about 110, 000 transistors and has a die area of 4.68mm * 4.96mm, and the system has the processing speed of about 50M pixels/sec.