• The Journal of Korean Institute of Next Generation Computing
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• v.13 no.3
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• pp.26-33
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• 2017

Recently container technologies have been receiving attention for efficient use of the cloud platform. Container virtualization technology has the advantage of a highly portable, high density when compared with the existing hypervisor. Container virtualization technology, however, uses a virtualization technology at the operating system level, which is shared by a single kernel to run multiple instances. For this reason, the feature of container is that the attacker can obtain the root privilege of the host operating system internal the container. Due to the characteristics of the container, the attacker can attack the root privilege of the host operating system in the container utilizing the vulnerability of the kernel. In this paper, we propose a framework for efficiently detecting and responding to root privilege attacks of a host operating system in a container. This framework uses a memory trap technique to detect changes in a specific memory area of a container and to suspend the operation of the container when it is detected.

• The KIPS Transactions:PartA
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• v.19A no.1
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• pp.35-44
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• 2012

Traditional technologies that are used to improve the performance of hard disk drives show many negative cases if they are applied to solid state drives (SSD). Access time and block sequence in hard disk drives that consist of mechanical components are very important performance factors. Meanwhile, SSD provides superior random read performance that is not affected by block address sequence due to the characteristics of flash memory. Practically, it is recommended to disable prefetching if a SSD is installed in a personal computer. However, this paper presents a combinational method of a prefetching scheme and a memory management that consider the internal structure of SSD and the characteristics of NAND flash memory. It is important that SSD must concurrently operate multiple flash memory chips. The I/O unit size of NAND flash memory tends to increase and it exceeded the block size of operating systems. Hence, the proposed prefetching scheme performs in an operating unit of SSD. To complement a weak point of the prefetching scheme, the proposed memory management scheme adaptively evicts uselessly prefetched data to maximize the sum of cache hit rate and prefetch hit rate. We implemented the proposed schemes as a Linux kernel module and evaluated them using a commercial SSD. The schemes improved the I/O performance up to 26% in a given experiment.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1996.10a
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• pp.58-63
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• 1996

A study is drawn up its result's tables and graphs by measuring tools(outside micrometer cylinder gauge and dial caliper gauge) on the difference of diameter volumes from before-discharge and after-discharge under 52 Kind's experimental condition by cupper and graphite electrode of CNC EDM. The EDM is attached with A.V.R. and memory scope for keep up accuracy and the fixed table of work piece is used in order to eliminate the noise by the internal resistance of it and forcing to eradicate the discharge liquid. It is analyzed cutting conditions to compare its wave value and pulse time.(Ton Toff) through voltage and current for decreasing working error.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.12
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• pp.1552-1564
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• 1995

A fault detecting method of ternary logic is proposed by using the spectral coefficients of the Chrestenson function. Fault detecting conditions are derived for a stuck-at fault in case of single input, multiple inputs and internal lines in the ternary logic. The detecting conditions for min/max bridging faults are also considered. When using this fault analysis method, it is possible to detect faults without the test vector and minimize high volume memory for storing the vector and response data. Thus, the computational complexity for the test vector can be decreased.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.15-16
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• 2007

In order to provide value-added services, next generation routers should perform packet classification for each incoming packet at wire-speed. In this paper, we proposed hierarchical priority trio (Hptrie) for packet classification. The proposed scheme improves the search performance and the memory requirement by replacing empty internal nodes in ordinary hierarchical trio with priority nodes which are the nodes including the highest priority rule among sub-trie nodes.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.707-710
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• 1998

This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a $0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is $20\muV/^{\circ}C,$ supply voltage dependency is $\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is $5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• Journal of Fisheries and Marine Sciences Education
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• v.29 no.2
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• pp.436-446
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• 2017

This study was performed to verify the validity and utility of the Korean Behavior Rating Inventory of Executive Function-Preschool Version(BRIEF-P). The BRIEF-P is one of the most used instruments to measure Executive Function(EF) and a teacher-rating assessment method designed to measure the executive function of preschoolers(age 2-5). A total of 200 preschoolers(104 boys, 96 girls; recruited aged 3 to 5years) participated. Confirmatory factor analysis was carried out to evaluate the model structure. Correlation analysis was done to verify the concurrent validity. In the results, the model fit indexes were good with the five BRIEF-P subscales (that is, inhibit, shift, emotional control, working memory, plan/organize). The internal consistency of the BRIEF-P five subscales were supported. As a results, the Korean Behavior Rating Inventory of Executive Function-Preschool Version(BRIEF-P) was confirmed to be a reliable and valid assessment tool to measure executive function in preschoolers.

• The Journal of Internal Korean Medicine
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• v.16 no.1
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• pp.1-16
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• 1995

This study was done in order to investigate the etiology and pathology of dementia in the variety literature. Dementia in elderly persons(above the age of 60) mainly classfied Alzheimer disease and Cerebral vascular dementia. The results were as follows: 1. Dementia patients have abnormal mental function, who have no mental weakness but defects of memory, verbal disturbance, behavior disturbance and loss of intellectual function. 2. Dementia regard as 'me-beng(?病)', 'jeon-gwang(癲狂)', and 'heo-ro(虛勞)' in oriental medicine and the symptom is a silence with no response, mixing, a crying or a laugh, a stranger behavior and a amnesia; disturbances of speech, emotion, behavior. 3. Dementia caused by Alzheimer disease, Multi infarct dementia, Parkinson's disease, sequelae of acute CO poisoning, head injury and alcoholism(occidental medically) and the 'Dam(痰) and Damhwa(痰火), weakness of heart and spleen(心脾虛) caused by pent up anger of seven emotions(七情鬱結), the weakness of liver and kidney(肝腎不足)(oriental medically). 4. The causes of Alzheimer disease are various; a heredity factor, a morphological factor of brain tissues, a psychological factor and a biochemical factor (occidental medically) ; the 'Dam(痰) and Damhwa(痰火) caused by weakness of the internal organs and disturbance of the emotions(oriental medically). 5. Cerebral vascular dementia caused by loss of the certain cerebral neurons and oriental medically caused by obstruction of 'dam(痰)' or 'eo heul(瘀血)'. It is recommended that further study of many sided investigations, specially against a weakness of spiritual functions and a certain neurotoxin in the future.