• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.19-24
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• 2016

Along the few nano sizing dimensions of integrated circuit (IC) devices, acceptable interlayer material for design is inevitable. The interlayer which include dielectric, interconnect, barrier etc. needs to achieve not only electrical properties, but also mechanical properties for endure post manufacture process and prolonging life time. For developing intermetallic dielectric (IMD) the mechanical issues with post manufacturing processes were need to be solved. For analyzing specific structural problem and material properties Raman spectroscopy was performed for various researches in Si semiconductor based materials. As improve of the laser and charge-coupled device (CCD) technology the total effectiveness and reliability was enhanced. For thin film as IMD developed material could be analyzed by Raman spectroscopy, and diverse researches of developing method to analyze thin layer were comprehended. Also In-situ analysis of Raman spectroscopy is introduced for material forming research.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.53-61
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• 1994

Intermetallic dielectric layer was formed by using SiO$_2$/SOG/SiO$_2$ for aluminum based dual-metal interconnection process and its electric characteristics were evaluated. The dielectric layer was in the cost and facility point of view more useful than the insulator that was formed by etch-back process. The planarity by using SOG process was about 40% higher than that of the insulator by the CVD process. When SiO$_2$ films were deposited by the PECVD process the Al hillock formation during the next process was restrained bucause the intermetalic insulator was made at low temperature. The leakage current was 1${\times}10^{7}~1{\times}10^{-8}A/cm^{2}$ at the electric field of 10$^{5}$V/cm and breakdown filed was 4.5${\times}10^{6}~7{\times}10^{6}A/cm$. So we had confirmed that siloxane SOG was very useful for intermetallic layer material.

• Journal of Korean Vacuum Science & Technology
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• v.7 no.2
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• pp.33-38
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• 2003

Fluorinated amorphous carbon thin films (a-C:F) for the use of low dielectric constant intermetallic layer dielectrics are deposited by plasma enhanced chemical vapor deposition with $C_4$F$_{8}$ and Si$_2$H$_{6}$/He gas mixture as precursors. To characterize and improve film properties, we changed various conditions such as deposition temperature, and RF power, and we measured the thickness and refractive indexes and FT-IR spectrum before and after annealing. At low temperatures the film properties were very poor although the growth rate was very high. On the other hand, the growth rate was low at high temperature. The growth rate increased in accordance with the deposition pressure. The dielectric constants of samples were in the range of 1.5∼5.5∼5.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.1-5
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• 2004

A multi-layer flexible substrate is composed of copper(Cu)/polyimide that are known as good electrical conductivity, and low dielectric constant, respectively. In this study. conductor line of $5{\mu}m$-pitch was successfully fabricated without non-uniform pattern shape by electroplating copper and coating polyimide on patterned stainless steel. For multi-layer flexible substrate, via holes were drilled by UV laser and filled with electroplating copper and tin. And then, the PI layer with vias and conductor lines was stripped from stainless steel substrate. The PI layers were laminated at once with careful alignment between layers. Solid state reaction between tin and copper during lamination formed the intermetallic compounds of $Cu_6Sn_5$($\eta$-phase) and $Cu_3Sn$($\epsilon$-Phase) and achieved a complete inter-connection by vertically positioning the plugged via holes on via pad. The via formation process has several advantages; such as better electrical property and lower cost than V type via and paste via.

• Journal of Sensor Science and Technology
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• v.4 no.3
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• pp.80-88
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• 1995

This paper presents the fabrication of a metal-insulator-metal(MIM) antifuse structure consisting of insulators sandwiched between top electrode, Al, and bottom electrode, TiW and additionally studies on antifuse properties depending on the condition of insulator. The intermetallic insulators, prepared by means of sputter, comprised of silicon oxide and tantalum oxide. In such an antifuse structure, silicon oxide layer is utilized to decrease the leakage current and tantalum oxide layer, of which the dielectric strength is lower than that of silicon oxide, is also utilized to lower the breakdown voltage near 10V. Finally sufficient low leakage current, below 1nA, and low programming voltage, about 9V, could be obtained in antifuse device comprising $Al/Ta_{2}O_{5}(10nm)/SiO_{2}(10nm)/TiW$ structure and OFF resistance of 3$3.65M{\Omega}$ and ON resistance of $7.26{\Omega}$ could be also obtained. This $Ta_{2}O_{5}/SiO_{2}$ based antifuse structures will be promising for highly reliable programmable device.