• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.5
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• pp.384-390
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• 2022

In this study, a single-stage, four-phase, interleaved, totem-pole AC-DC converter is proposed for a super-fast charger station that requires high power, a wide voltage range, and bidirectional operation capabilities and adopts various types of electric transport vehicles. The proposed topology is based on current-fed push-pull dual active bridge converter combined with the totem-pole operation. Owing to the four-phase interleaving effect, the bridge on the grid side can switch at 0.25, 0.5, and 0.75 to achieve a ripple-free grid current. The input filter can be removed theoretically. Switching methods for the duty of the secondary-side duty cycle are proposed, and they correspond to the primary duty cycle for reducing the circulating power and handling the total harmonic distortion. Therefore, the converter can operate under a wide voltage range. Experimental results from a 7.5 kW prototype are used to validate the proposed concept.

• Journal of IKEEE
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• v.26 no.3
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• pp.506-509
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• 2022

In a secret sharing scheme, secret information must be distributed and stored to users, and confidentiality must be able to be reconstructed only from an authorized subset of users. To do this, secret information among different code words must not be subordinate to each other. The minimal code is a kind of linear block code to distribute these secret information not mutually dependent. In this paper, we present a novel extension technique for minimal codes. The product of an arbitrary vector and a minimal code produces a new minimal code with an extended length and Hamming weight. Accordingly, it is possible to provide minimal codes with parameters not known in the literature.

• Current Optics and Photonics
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• v.7 no.2
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• pp.157-165
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• 2023

We propose a highly directional waveguide grating antenna for an optical phased array, achieving high directionality of more than 97% by interleaving the trenches with different etching depths in the silicon nitride layer, and adopting a multilayered structure. Meanwhile, the multilayered structure reduces the perturbation strength, which enables a centimeter-scale radiation length. The beam-steering range is 13.2°, with a wavelength bandwidth of 100 nm. The 1-dB bandwidth of the grating is 305 nm. The multilayered grating structure has a large tolerance to the fabrication variation and is compatible with CMOS fabrication techniques.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.184-190
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• 2002

This paper compares and analyzes and analyzes the transmission performance of the OpenCable system and the DBD-C system which are adopted as the digital CATV transmission standard in U.S.A. and Europe respectively through computer simulation under the same channel environment. We considered the channel environment including the random noise and the CTB (Composite Tripple Beats) noise as channel impairments in order to compare the two standard fairly. Additionally, we analyzed the transmission performance of the OpenCable system for the various interleaving depths. We implemented each transmission system by software, and we analyzed BER values with respect to the C/N in order to compare their transmission performance. As a result of the computer simulation, to get the BER of ${10}^{-6}$ the OpenCable system requires 1.2 dB kiwer C/N than the DVB-C system in the 64-QAM mode, and the two system require similar C/N in the 256-QAM mode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.63-72
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• 2012

In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.2
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• pp.199-208
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• 2014

Code division multiple access (CDMA) is one of the promising medium access control (MAC) schemes for underwater acoustic sensor networks because of its robustness against frequency-selective fading and high frequency-reuse efficiency. As a way of performance evaluation, sea or lake experiment has been employed along with computer simulation.. In this study, we design the underwater CDMA forward-link transceiver and evaluate the feasibility aginst harsh underwater acoustic channel in water-tank first. Then, based on the water-tank experiment results, we improved the transceiver and showed the improvements in a lake experiment. A pseudo random noise code acquisition process is added for phase error correction before decoding the user data by means of a Walsh code in the receiver. Interleaving and convolutional channel coding scheme are also used for performance improvement. Experimental results show that the multiplexed data is recovered by means of demultiplexing at receivers with error-free in case of two users while with less than 15% bit error rate in case of three and four users.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.111-120
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• 2011

Data mining algorithms should exploit new hardware technologies to accelerate computations. Such goal is difficult to achieve in database management system (DBMS) due to its complex internal subsystems and because data mining numeric computations of large data sets are difficult to optimize. This paper explores taking advantage of existing multithreaded capabilities of multicore CPUs as well as caching in RAM memory to efficiently compute summaries of a large data set, a fundamental data mining problem. We introduce parallel algorithms working on multiple threads, which overcome the row aggregation processing bottleneck of accessing secondary storage, while maintaining linear time complexity with respect to data set size. Our proposal is based on a combination of table scans and parallel multithreaded processing among multiple cores in the CPU. We introduce several database-style and hardware-level optimizations: caching row blocks of the input table, managing available RAM memory, interleaving I/O and CPU processing, as well as tuning the number of working threads. We experimentally benchmark our algorithms with large data sets on a DBMS running on a computer with a multicore CPU. We show that our algorithms outperform existing DBMS mechanisms in computing aggregations of multidimensional data summaries, especially as dimensionality grows. Furthermore, we show that local memory allocation (RAM block size) does not have a significant impact when the thread management algorithm distributes the workload among a fixed number of threads. Our proposal is unique in the sense that we do not modify or require access to the DBMS source code, but instead, we extend the DBMS with analytic functionality by developing User-Defined Functions.

• Journal of KIISE:Software and Applications
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• v.27 no.2
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• pp.108-119
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• 2000

Most of prior works on testing parallel programs have concentrated on how to guarantee the reproducibility by employing event traces exercised during executions of a program. Consequently, little work has been done to generate meaningful event sequences, especially, from specifications. This paper describes techniques for deriving event sequences from Message Sequence Charts(MSCs) which are widely used in telecommunication areas for its simplicity in specifying the behaviors of a program. For deriving event sequences from MSCs, we have to uncover the causality relations among events embedded implicitly in MSCs. In order to attain this goal, we adapt vector time stamping which has been previously used to determine the ordering of events taken place during an execution of interacting processes. Then, valid event sequences, satisfying the causality relations, are generated according to the interleaving rules suggested in this paper. The feasibility of our testing technique was investigated using the phone conversation example. In addition, we discussed on the experimental results gained from the example and how to combine various test criteria into our testing environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1372-1382
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• 1999

The major source of errors in high-speed networks such as Broadband ISDN(B-lSDN) is buffer overflow during congested conditions. These congestion errors are the dominant sources of errors in 1high-speed networks and result in cell losses. Conventional communication protocols use error detection and retransmission to deal with lost packets and transmission errors. However, these conventional ARQ(Automatic Repeat Request) methods are not suitable for the high-speed networks since the transmission delay due to retransmissions becomes significantly large. As an alternative, we have presented a method to recover consecutive cell losses using forward error correction(FEC) in ATM(Asynchronous Transfer Mode)networks to reduce the problem. The performance estimation based on the cell discard process model has showed our method can reduce the cell loss rate substantially. Also, the performance estimations in ATM networks by interleaving and IP multicast service are discussed.

• The Transactions of the Korea Information Processing Society
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• v.5 no.10
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• pp.2686-2703
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• 1998

The widening pClformnnce gap between processor and memory causes an emergence of the promising architecture, processor-memory (PM) integration In this paper, various design issues for P-M integration are studied, First, an analytical model of the DRAM access time is constructed considering both the bank conflict ratio and the DRAM page hit ratio. Then the points of both the performance improvement and the perfonnance bottle neck are found by the proposed model as designing on-chip DRAM architectures. This paper proposes the new architecture, called the delayed precharge bank architecture, to improve the perfonnance of memory system as increasing the DRAM page hit ratio. This paper also adapts an efficient bank interleaving mechanism to the proposed architecture. This architecture is verified !II he better than the hierarchical multi-bank architecture as well as the conventional bank architecture by executiun driven simulation. Eight SPEC95 benchmarks are used for simulation as changing parameters for the cache architecture, the number of DRAM banks, and the delayed time quantum.