• Proceedings of the KSME Conference
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• 2000.04a
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• pp.760-765
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• 2000

The study deals with the development of a computational procedure for evaluating the temperature rise in dry and lubricated multi-layered contacts of head/disk interface. A transient computational model with a transformed rectangular computational domain is utilized. A model and a computational method for micro-contact with sub-lubricated zone, including friction heat generation, have been presented. The model was applied, taking full account of the changes in contact area and contact load due to frictional heating. The computational distribution of temperature is obtained with the analytical findings for various composition and contact conditions. Especially, a rapid rise ($220^{\circ}C$ or above) in read head temperature lese to a saturation in the influence of a thermal spike on signal performance. This general class of problems can be treated provided that heat generation distribution and layer properties are known.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2003.11a
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• pp.97-104
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• 2003

The surface temperature at the interface of bodies in a sliding contact is one of the most important factors influencing the behavior of machine components. So the calculation of the surface temperature at a sliding contact interface has long been an interesting and important subject for tribologist. In this study to verify estimation of temperature rising, calculated temperatures were compared with measured temperatures. It is possible to calculate bulk and flash temperature.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2001.11a
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• pp.260-266
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• 2001

The surface temperature at the interface of bodies in a sliding contact is one of the most important factors influencing the behavior of machine components. So the calculation of the surface temperature at a sliding contact interface has long been an interesting and important subject for tribologist. Several methods for calculating surface temperature have been devised. Several numerical methods have been used to predict the temperature rise of sliding surface. but those need much time to calculate. In this study to reduce the calculation time the hybrid method using both semi-infinite solid analysis and FVM was used. It is founded that the computing time of hybrid method was shorter than that of FVM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.3
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• pp.181-185
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• 2003

Influence of post gate oxidation anneal on Negative Bias Temperature Instability (NBTI) of PMOSFE has been investigated. At oxidation anneal temperature raised above 950$^{\circ}$C, a significant improvement of NBTI was observed which enables to reduce PMO V$\_$th/ shift occurred during a Bias Temperature (BT) stress. The high temperature anneal appears to suppress charge generations inside the gate oxide and near the silicon oxide interface during the BT stress. By measuring band-to-band tunneling currents and subthreshold slopes, reduction of oxide trapped charges and interface states at the high temperature oxidation anneal was confirmed.

• 한국신재생에너지학회:학술대회논문집
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• 2009.06a
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• pp.172-175
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• 2009

n-type crystalline silicon wafers were passivated with intrinsic a-Si:H thin films on both sides using HWCVD. Minority carrier lifetime measurement was used to verify interface passivation properties between a-Si:H thin film and crystalline Si wafer. Thin film interface characteristics were investigated depending on $H_2/SiH_4$ ratio and hot wire deposition temperature. Vacuum annealing were processed after deposition a-Si:H thin films on both sides to investigate thermal effects from post process steps. We noticed the effect of interface passivation properties according to $H_2/SiH_4$ ratio and hot wire deposition temperature, and we had maximum point of minority carrier lifetime at H2/SiH4 10 ratio and $1600^{\circ}C$ wire temperature.

• Journal of the Korean Ceramic Society
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• v.34 no.8
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• pp.825-833
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• 1997

Silicon carbide films were deposited by low pressure chemical vapor deposition(LPCVD) using MTS(CH3SICl3) in hydrogen atmosphere on (100) Si substrate. To prevent the unstable interface from being formed on the substrate, the experiments were performed through three deposition processes which were the deposition on 1) as received Si, 2) low temperature grown SiC, and 3) carbonized Si by C2H2. The microstructure of the interface between Si substrates and SiC films was observed by SEM and the adhesion between Si substrates and SiC films was measured through scratch test. The SiC films deposited on the low temperature grown SiC thin films, showed the stable interfacial structures. The interface of the SiC films deposited on carbonized Si, however, was more stable and showed better adhesion than the others. In the case of the low temperature growth process, the optimum condition was 120$0^{\circ}C$ on carbonized Si by 3% C2H2, at 105$0^{\circ}C$, 5 torr, 10 min, showed the most stable interface. As a result of XRD analysis, it was observed that the preferred orientation of (200) plane was increased with Si carbonization. On the basis of the experimental results, the models of defect formation in the process of each deposition were compared.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.465-468
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• 1987

This paper describes a model to calculate the equilibrium electron density of MODFET at the interface that takes into account the simultaneous shallow and deep level in the Al-GaAs layer. In the present study we have made an investigation of the interface electron density with different values of the AlGaAs doping density and spacer layer thickness, considering simultaneously two doner levels. In this case, the ratio of the shallow to the deep donor concentraction is considered. From the comparison with early experimental results we could find the deep level and that the deep donor concentration is about 50% with the Al mole fraction X ${\sim}0.3$, activation energy Edx=65meV, temperature $77^{\circ}K$ and spacer thickness range $50A{\sim}100A$. Also we have investigated the effect of the temperature. As temperature increase, at critical mole fraction X the nature of the donor concentration changes from $\Gamma$ to L and X.

• Journal of Welding and Joining
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• v.31 no.3
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• pp.76-83
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• 2013

This study investigated the effect of bonding temperature and holding time on microstructures and mechanical properties of diffusion bonded joint of Haynes230. The diffusion bonds were performed at the temperature of 950, 1050, and $1150^{\circ}C$ for holding times of 30, 60, 120 and 240 minutes at a pressure of 4MPa under high vacuum condition. The amount of non-bonded area and void observed in the bonded interface decreased with increasing bonding temperature and holding time. Cr-rich precipitates at the linear interface region restrained grain migration at $950^{\circ}C$ and $1050^{\circ}C$. However, the grain migration was observed in spite of short holding time due to the dissolution of precipitates to base metal in the interface region at $1150^{\circ}C$. Three types of the fracture surface were observed after tensile test. The region where the coalesce and migration of grain occurred much showed high fracture load because of base metal fracture whereas the region where those did less due to the precipitates demonstrated low fracture load because of interface fracture. The expected fracture load could be derived with the value of fracture area of base metal ($A_{BF}$) and interface ($A_{IF}$), $Load=201A_{BF}+153A_{IF}$. Based on this equation, strength of base metal and interface fracture were calculated as 201MPa and 153MPa, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.101-105
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• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1791-1794
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• 2006

For system-on-glass (SoG) with low-temperature poly-silicon (LTPS) thin film transistor (TFT), a new system interface architecture and timing controller are developed. With the newly developed system interface architecture, line memory can be eliminated which would take large area of SoG display panel. The system interface and timing controller are targeted for the application for 6-bit gray scale, 60-frames/s qVGA format.