• 한국전기전자재료학회논문지
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• 제15권2호
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• pp.127-132
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• 2002

Space charge distributions and behaviors in silane crosslinked polyethylene(SXLPE)/ crosslinked polyethylene(XLPE) laminates were investigated using a pulsed electroacoustic (PEA) method. In case of monolayer, XLPE shows heterocharge while SXLPE shows homocharge. It was observed that charges were accumulated at the interface of SXLPE/XLPE laminate when applied electric field was more than 20kV/mm. The charge profile at various temperatures was also acquired using temperature-controllable PEA system. Although applied electric field is only 8.6 kV.mm, positive interfacial charge starts to appear near 50$^{\circ}C$. It was found that the interfacial charge behavior of SXLPE/XLPE laminate under low voltage at high temperature is corresponding to that under high voltage at room temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.68-69
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• 2011

The process of charge transfer at the interface between two semiconductors or between a metal and a semiconductor plays an important role in many areas of technology. The optimization of such devices requires a good theoretical description of the interfaces involved. This, in turn, has motivated detailed mechanistic studies of interfacial charge-transfer reactions at metal/organic, organic/organic, and organic/inorganic semiconductor heterojunctions. Charge recombination of photo-induced electron with redox species such as oxidized dyes or triiodide or cationic HTM (hole transporting materials) at the heterogeneous interface of $TiO_2$ is one of main loss factors in liquid junction DSSCs or solid-state DSSCs, respectively. Among the attempts to prevent recombination reactions such as insulating thin layer and lithium ions-doped hole transport materials and introduction of co-adsorbents, although co-adsorbents retard the recombination reactions as hydrophobic energy barriers, little attention has been focused on the anchoring processes. Molecular engineering of heterogeneous interfaces by employing several co-adsorbents with different properties altered the surface properties of $TiO_2$ electrodes, resulting to the improved power conversion efficiency and long-term stability of the DSSCs. In this talk, advantages of the coadsorbent-assisted sensitization of N719 in preparation of DSSCs will be discussed.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.72-72
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• 2010

Recent development of organic solar cell approaches the level of 8% power conversion efficiency by the introduction of new materials, improved material engineering, and more sophisticated device structures. As for interface engineering, various interlayer materials such as LiF, CaO, NaF, and KF have been utilized between Al electrode and active layer. Those materials lower the work function of cathode and interface barrier, protect the active layer, enhance charge collection efficiency, and induce active layer doping. However, the addition of another step of thin layer deposition could be a little complicated. Thus, on a typical solar cell structure of Al/P3HT:PCBM/PEDOT:PSS/ITO glass, we used Li:Al alloy electrode instead of Al to render a simple process. J-V measurement under dark and light illumination on the polymer solar cell using Li:Al cathode shows the improvement in electric properties such as decrease in leakage current and series resistance, and increase in circuit current density. This effective charge collection and electron transport correspond to lowered energy barrier for electron transport at the interface, which is measured by ultraviolet photoelectron spectroscopy. Indeed, through the measurement of secondary ion mass spectroscopy, the Li atoms turn out to be located mainly at the interface between polymer and Al metal. In addition, the chemical reaction between polymer and metal electrodes are measured by X-ray photoelectron spectroscopy.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.37-40
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• 1999

For the first time, charge trapping nonvolatile semiconductor memories with the deoxidized oxynitride gate dielectric is proposed and demonstrated. Gate dielectric wit thickness of less than 1 nm have been grown by postnitridation of pregrown thermal silicon oxides in NO ambient and then reoxidation. The nitrogen distribution and chemical state due to NO anneal/reoxidation were investigated by M-SIMS, TOF-SIMS, AES depth profiles. When the NO anneal oxynitride film was reoxidized on the nitride film, the nitrogen at initial oxide interface not only moved toward initial oxide interface, but also diffused through the newly formed tunnel oxide by exchange for oxygen. The results of reoxidized oxynitride(ONO) film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/N-rich SiON interface/Si-rich SiON(nitrogen diffused tunnel oxide)/Si substrate. In addition, the SiON and the S1$_2$NO Phase is distributed mainly near the tunnel oxide, and SiN phase is distributed mainly at tunnel oxide/Si substrate interface.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.299-301
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• 1997

It was investigated that space charge characteristics of EPDM/XLPE laminates as a function of interfacial condition. There were no effects in charge accumulation characteristics at EPDM/XLPE laminate samples pasted treated silicone oil and silicone grease. But when the crosslinking coagent (TMPTA) was pasted in laminate samples, there was no space charge in interface of EPDM/XLPE laminate. There were no effects in the laminate sample pasted silicone grease dissolved crosslinking coagent. In the coupling agent pasted EPDM/ XLPE laminate sample, space charge was accumulated in XLPE side caused by coupling agent.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.140-143
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• 1997

It was investigated that space charge characteristics of EPDX/LPE laminates as a function of interfacial condition. There were no effects in charge accumulation characteristics at EPDM/XLPE laminate samples which were pasted with silicone oil and silicone grease. But when the crosslinking coagent (TMPTA) was pasted in laminate samples, there was no space charge in interface of EPDE/XLPE laminate and no effects in the laminate sample pasted with silicone grease dissolved crosslinking coagent. In the coupling agent pasted EPDhyXLPE laminate sample, space charge was accunlulated in XLPE side caused by coupling agent.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권9호
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• pp.502-509
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• 2000

In this paper in order to evaluat quantitavely the formation mechanism of space charge and its effects on the conduction characteristics in LDPE we have carried out the numerical analysis on the basis of experimental results of space charge distribution cathode field and current with time which had been simultaneously measured at applied field of 50kV/mm and room temperature. As the models for numerical analysis we employ the Richarson-Schottky theory for charge injection from electrode into LDPE and the band-tail conduction at crystalline regions and the hopping conduction by traps which mainly exist at the interface regions of crystalline-amorphous region for charge transport in LDPE. Futhermore in order to investigate the influence of physical parameters on the time characteristcs of space charge distribution and measured current we have changed the values of trap density activation energies for charge injection and transport and have analyzed their effects.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1268-1270
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• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• 한국재료학회지
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• 제19권9호
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• pp.462-467
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• 2009

The Charge Trap Flash (CTF) memory device is a replacement candidate for the NAND Flash device. In this study, Pt/$Al_2O_3/La_2O_3/SiO_2$/Si multilayer structures with lanthanum oxide charge trap layers were fabricated for nonvolatile memory device applications. Aluminum oxide films were used as blocking oxides for low power consumption in program/erase operations and reduced charge transports through blocking oxide layers. The thicknesses of $SiO_2$ were from 30 $\AA$ to 50 $\AA$. From the C-V measurement, the largest memory window of 1.3V was obtained in the 40 $\AA$ tunnel oxide specimen, and the 50 $\AA$ tunnel oxide specimen showed the smallest memory window. In the cycling test for reliability, the 30 $\AA$ tunnel oxide sample showed an abrupt memory window reduction due to a high electric field of 9$\sim$10MV/cm through the tunnel oxide while the other samples showed less than a 10% loss of memory window for $10^4$ cycles of program/erase operation. The I-V measurement data of the capacitor structures indicated leakage current values in the order of $10^{-4}A/cm^2$ at 1V. These values are small enough to be used in nonvolatile memory devices, and the sample with tunnel oxide formed at $850^{\circ}C$ showed superior memory characteristics compared to the sample with $750^{\circ}C$ tunnel oxide due to higher concentration of trap sites at the interface region originating from the rough interface.