• Title/Summary/Keyword: interconnection network

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Evaluation of Optimal Transfer Capability in Power System interconnection (연계된 계통간의 최적 송전용량 산정)

  • Son, Hyun-Il;Choi, Ah-Reum;Lee, Sung-Hoon;Kim, Jin-O;Jeon, Dong-Hoon
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.195_196
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    • 2009
  • As the electrical power industry is restructured, the electrical power exchange is becoming extended. One of the key information used to determine how much power can be transferred through the network is known as available transfer capability (ATC). To calculate ATC, traditional deterministic approach is based on the severest case, but the approach has the complexity of procedure. Therefore, novel approach for ATC calculation is proposed using cost-optimization method in this paper, and is compared with well-being method and risk-benefit method. This paper proposes the optimal transfer capability of HVDC system between mainland and a separated island in Korea through these three methods. These methods will consider production cost, wheeling charge through HVDC system and outage cost with one depth (N-1 contingency).

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Robust Adaptive Position Control for Servomotor Drive Using Fuzzy-neural Networks (퍼지 뉴럴 네트워크를 이용한 서보모터 드라이브의 강인 적응 위치 제어)

  • Hwang, Young-Ho;Lee, An-Yong;Kim, Hong-Pil;Yang, Hai-Won
    • Proceedings of the KIEE Conference
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    • 2006.07d
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    • pp.1834-1835
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    • 2006
  • A robust adaptive position control algorithm is proposed for servomotor drive system with uncertainties and load disturbance. The proposed controller is comprised of a nominal controller and a robust control. The nominal controller is designed in the condition without all the external load disturbance, nonlinear friction and unpredicted uncertainties. The robust controller containing lumped uncertainty approximator using fuzzy-neural network(FNN) is designed to dispel the effect of uncertainties and load disturbance. The interconnection weight of the FNN can be online tuned in the sense of the Lyapunov stability theorem thus asymptotic stability of the proposed control system can be guaranteed. Finally, simulation results verify that the proposed control algorithm can achieve favorable tracking performance for the induction servomotor drive system.

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Simulation Studies on Monitoring System for Interconnection of Distibuted Generation to Power Grid (분산전원 계통 연계 상황 모니터링을 위한 시뮬레이션 연구)

  • Oh, Sung-Nam;Han, Chul-Wan;Yoon, Ki-Don;Son, Young-Ik;Kim, Kab-Il
    • Proceedings of the KIEE Conference
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    • 2005.05a
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    • pp.96-98
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    • 2005
  • This paper describes a monitoring system that monitors power quality and undesirable accidents when distributed generations are connected to the power grid. Prior to develop and operate a physical monitoring system, we constitute a simulation device to simulate the monitoring processes for the situations. The simulation system consists of the server and the client that connected by communication line. This system has various functions to monitor the power quality and the connection situation. Those functions are generation, transmission, acquisition and analysis of the simulated power data. This research seems very important to get the reliable and intelligent connection algorithm through the result of simulated monitoring system. Also hereafter, as this system uses the remote monitoring system through network and constitute the data base(DB), it will play an important role in building the automation of power system efficiently and systematically.

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Design of A Logic/Timing Extraction System for Higher-level Design Verification (상위단계 설계 검증을 위한 논리/타이밍 추출 시스템의 설계)

  • 이용재;문인호;황선영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.2
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    • pp.76-85
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    • 1993
  • This paper describes the design of a technology-independent logic, function, and timing extraction system from SPICE-like network descriptions. Technology-independent extraction mechanism is provided in the form of technology files containing the rules for constructing logic gates and functional blocks. The designed system can be more effectively used in cell-based design by describing the cells to be extracted. Timing extraction is performed by using a linear RC gate delay model which takes interconnection delay into account. Experimental results show that estimated delay is within 10 percents for logic gate circuits when compared with SPICE. Through higher-level design descriptions obtained by extraction, design cycles can be considerably reduces.

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An Approximation Scheme For A Geometrical NP-Hard Problem (기하학적 NP-hard 문제에 대한 근사 접근법)

  • Kim, Joon-Mo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.8
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    • pp.62-67
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    • 2007
  • In some wireless sensor networks, the sensor nodes are required to be located sparsely at designated positions over a wide area, introducing the problem of adding minimum number of relay nodes to interconnect the sensor nodes. The problem finds its form in literature: the Minimum number of Steiner Points. Since it is known to be NP-hard, this paper proposes an approximation scheme to estimate the minimum number of relay nodes through the properties of the abstract from. Reducing the number of nodes in a sensor network, the amount of data exchange over the net will be far decreased.

An Interconnection Plane for Network Reliability and Interoperability (통신망 신뢰성 및 상호운용성 확보를 위한 상호접속방안)

  • 조평동;김용환;이영환;신송섭;강영홍
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1998.11a
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    • pp.344-349
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    • 1998
  • 본 논문에서는 통신망 신뢰성 및 상호운용성 확보를 위한 상호접속 방안을 고찰하였다. 이를 위해 국내외의 상호접속 관련법 현황 및 상호접속관련 표준기관 분석을 행하였고, 상호접속의 기본개념 및 상호접속의 예와 관련 표준들의 정립을 통한 상호접속 방안을 분석하였다. 그 방안으로서 규제기관 산하의 위원회를 통한 상호접속계획 처리, 상호접속협정, 운용 및 표준개발에 대한 모델정립이 필요하며, 특히 글로벌 초고속 통신망 구현을 위한 국제 표준기판과의 협력이 절실히 요구되고 있다. 분 연구의 결과는 향후 국내의 상호접속 관련 표준개발 및 운용 등의 기초자료로써 활용될 것이다.

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Application Analysis of a Resistive type SFCL for Transmission Systems (EMTCD를 이용한 154kV 송전계통에서의 초전도 한류기 적용 해석)

  • Heo Tae Jeon;Bae Hyeong Thaek;Park Min Won;Yu In Keun
    • Proceedings of the KIEE Conference
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    • summer
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    • pp.409-411
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    • 2004
  • The need for Fault Current Limiters (FCL) is associated with the continuous growth and interconnection of modem power systems and increase in dispersed generation facilities, which result in progressive increase in the short circuit capacity far beyond their original design capacity. Fault Current Limiters (FCL) clips the fault currents and reduces the electromechanical stresses on the network and the need to handle excessive fault currents. In addition, the reduction of the fault duration Provided by the limiter should increase the power transmission capability and improve the dynamic stability. This paper proposes the model of resistive type superconducting fault current limiter using EMTDC(Electromagnetic transients for DC analysis program). In order to verify the effectiveness of the SFCL, in this paper, the analysis of fault current in a transmission system through the EMTDC based simulation by using the modeled component of a resistive type SFCL is peformed and the detailed results are given.

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Parallel Genetic Algorithm based on a Multiprocessor System FIN and Its Application to a Classifier Machine

  • 한명묵
    • Journal of the Korean Institute of Intelligent Systems
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    • v.8 no.5
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    • pp.61-71
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    • 1998
  • Genetic Algorithm(GA) is a method of approaching optimization problems by modeling and simulating the biological evolution. GA needs large time-consuming, so ti had better do on a parallel computer architecture. Our proposed system has a VLSI-oriented interconnection network, which is constructed from a viewpoint of fractal geometry, so that self-similarity is considered in its configuration. The approach to Parallel Genetic Algorithm(PGA) on our proposed system is explained, and then, we construct the classifier system such that the set of samples is classified into weveral classes based on the features of each sample. In the process of designing the classifier system, We have applied PGA to the Traveling Salesman Problem and classified the sample set in the Euclidean space into several categories with a measure of the distance.

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Cost-effective multistage interconnection network for UNMA model system (NUMA(non-uniform memory access) 모델 시스템을 위한 cost-effective한 다단계 상호연결망)

  • 최창훈;김성천
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.5
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    • pp.19-32
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    • 1997
  • So far, the multiple path MINs to provide redundant paths in the traditional UPP MINs have been realized by adding additional hardware such as extra stages, duplicated data links, or multiple copies of sthe MIN. And the traditional MINs do not exploit locality: communication with all processor-memory paris takes the same amount of time. Also so far there has been little progress for exploiting locality of reference in MINs. In this paper, we present a new topology MIN, hybrid MIN that is constructed with 2N-3 SEs which is far fewer SEs than that of traditional MINs. Although the hybrid MIN is constructed with 2N-3 SEs, the hybrid MIN satisfies full access capability (FAC) and has redundant paths(but providing single path for 2 memory modules of each processor). Moreover the has redundant paths (but providing single path for 2 memory modules of each processor). Moreover the Hybrid MIN provides shortcut path between pairs which have frequent dat acommunication (locality of reference). Its performance under varing degrees of localized communication is analyzed.

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Fault Diagnosis of Multistage Baseline Network (다단 베이스라인 네트워크의 오류진단)

  • Oh, Jae-Chul
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.6
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    • pp.860-867
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    • 1986
  • It was shown previously that four tests are required in order to detect single fault and to locate single link stuck fault for a class of multistage interconnection networks. In this paper, we show that only three tests are necessary and sufficient both to detect single fault and to locate single link stuck fault. A fault diagnosis method with four valid state for a class of multistage kinterconnection networks is presented. Using this method, all single link stuck fault or all single switching element faults, can be detected by at most 4 log2N+e tests. In the example, the location and type of single fault are pinpointed, and unlocatable probabilities of questionable of questionable regions are given.

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