• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.612-614
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• 1998

As chip feature size decrease, interconnect delay gains more importance. A accurate timing analysis required to estimate interconnect delay as well as cell delay. In this paper, we present a timing-level delay calculation tool of which the accuracy is bounded within 10% of SPICE results. This delay calculation tool generates delay values in SDF(Standard Delay Format) for parasitic data extracted in SPEF(Standard Parasitic Exchange Format). The efficiency of the tool is easily seen because it uses AWE(Asymptotic Waveform Evaluation) algorithm for interconnect delay calculation, and precharacterized library and effective capacitance model for cell delay calculation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.69-77
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• 2004

An efficient board-level interconnect test algorithm is proposed considering both the ground bounce effect and the delay fault detection. The proposed algorithm is capable of IEEE 1149.1 interconnect test, negative ground bounce effect prevention, and also detects delay faults as well. The number of final test pattern set is not much different with the previous method, even our method enables to detect the delay faults in addition to the abilities the previous method guarantees.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.1-8
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• 2000

In this paper, the dependence of interconnect line-induced delay time on the size of CMOSFET gate width is characterized. In case of capacitance dominant interconnect line, the total delay time decreases as transistor size increases. However, there exists a transistor size for minimum total delay time when both of resistance and capacitance of interconnect line become larger than those of transistor. The optimum transistor size for minimum total delay time is obtained using an analytic equation and the experimental results showed good agreement with the calculation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.59-68
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• 1999

The timing characteristics of an ASIC are analyzed based on the propagation delays of each gate and interconnect wire. The gate delay can be modeled using the two-dimensional delay table whose index variables are the input transition time and the output load capacitance. The AWE technique can be adopted as an algorithm to compute the interconnect delay. Since these delays are affected by the interaction to the two-dimensional delay table and the AWE technique. A method to model this effect has been proposed through the effective capacitance and the gate driver model under the assumption of single driving gate. This paper presents a new technique to handle the multiple CMOS gates driving interconnect wire by extending previous approach. This technique has been implemented in C language and applied to several interconnect circuits driven by multiple CMOS gates. In most cases, we found a few tens of speed-up and only a few percents of errors in computing both of gate and interconnect delays, compared to SPICE.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.8-13
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• 2009

In this paper, discontinuous interconnect lines are modeled as a cascaded line composed of many uniform interconnect lines. The system functions of respective uniform interconnect lines are determined, followed by its time domain response. Since the time domain response expression is a transcendental form, the waveform expression is reconfigured as an approximated linear expression. The proposed model has less than 2% error in the delay estimation.

• ETRI Journal
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• v.30 no.3
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• pp.403-411
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• 2008

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.824-831
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• 2014

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.101-112
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• 2004

In this paper, we developed a numerical analysis model by using ADI-FDTD method to analyze three-dimensional interconnect structure. We discretized maxwell's curl equation by using ADI-FDTD. Using ADI-FDTD method, a sampler circuit designed from 3.3 V CMOS technology is simplified to 3-metal line structure. Using this simplified structure, the time delay and signal distortion of complex interconnects are investigated. As results of simulation, 5∼10 ps of delay time and 0.1∼0.2 V of signal distortion are measured. As demonstrated in this paper, the full-wave analysis using ADI-FDTD exhibits a promise for accurate modeling of electromagnetic phenomena in high-speed VLSI interconnect.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.8
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• pp.1024-1030
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• 1999

IEEE 1149.1 바운다리스캔은 보드 수준에서 고장점검 및 진단을 위한 테스트 설계기술이다. 그러나, 바운다리스캔 제어기의 특성상 테스트 패턴의 주입에서 관측까지 2.5 TCK가 소요되므로, 연결선상의 지연고장을 점검할 수 없다. 본 논문에서는 UpdateDR 신호를 변경하여, 테스트 패턴 주입에서 관측까지 1 TCK가 소요되게 함으로써, 지연고장 점검을 가능하게 하는 기술을 소개한다. 나아가서, 정적인 고장점검을 위한 테스트 패턴을 개선해 지연고장 점검까지 가능하게 하는, N개의 net에 대한 2 log(n+2) 의 새로운 테스트패턴도 제안한다. 설계와 시뮬레이션을 통해 지연고장 점검이 가능함을 확인하였다.Abstract IEEE 1149.1 Boundary-Scan is a testable design technique for the detection and diagnosis of faults on a board. However, since it takes 2.5TCKs to observe data launched from an output boundary scan cell due to inherent characteristics of the TAP controller, it is impossible to test delay defects on the interconnect nets. This paper introduces a new technique that postpones the activation of UpdateDR signal by 1.5 TCKs while complying with IEEE 1149.1 standard. Furthermore we have developed 2 log(n+2) , where N is the number of nets, interconnect test patterns to test delay faults in addition to the static interconnect faults. The validness of our approach is verified through the design and simulation.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.67-75
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• 1998

This paper examined the geometrical variables of microstrip to control the characteristic impedance of MCM interconnect and also with respect to the practical requirements, evaluated the critical lengths for attenuation, propagation delay, and crosstalk at 500 MHz frequency compared to at 50 MHz frequency. With the illustration of each MCM-L and MCM-D interconnect having 50 characteristic impedance, it was revealed that the most important geometrical variables to control the characteristic impedance of microstrip are eventually dielectric thickness and line width. In particular, the dielectric thickness of MCM-D interconnect must be controlled with tolerance below 2 m. It is clear that the attenuation does not give rise to signal distortion in the range of up to 500MHz frequency for both MCM-L and MCM-D interconnects. However, the propagation delay is so significant that both MCM-L and MCM-D interconnects should be matched with load at the 500 MHz frequency. For the MCM-D interconnect, the crosstalk voltage would not be high to generate the wrong signal on the neighboring line at 500 MHz frequency, but the MCM-L interconnect could not be used due to severe crosstalk. Eventually, it is clear that the transmission line behavior must be studied for the design of MCM substrate at the 500 MHz frequency.