• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.188-188
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.

• 한국분말재료학회지
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• 제17권2호
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• pp.123-129
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• 2010

The fabrication of interconnect from titanium powders and $TiN_x$ powders is investigated. Corrosion-resistant titanium and $TiN_x$ are used as reinforcement in order to reveal high heat and corrosion resistance at the elevated temperature. We fabricated the plates for interconnect reinforced with $TiN_x$ by mixing titanium powders with 10 wt.% of nano-sized $TiN_x$. Spark Plasma Sintering (SPS) was chosen for the sintering of these composites. The plate made of titanium powders and $TiN_x$ powders demonstrates higher corrosion resistance than that of the plate of titanium powders alone. The physical properties of specimens were analyzed by performing hardness test and biaxial strength test. The electrochemical properties, such as corrosion resistance and hydrogen permeability at high temperature, were also investigated. The microstructures of the specimens were investigated by FESEM and profiles of chemical compositions were analyzed by EDX.

• 한국세라믹학회지
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• 제42권12호
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• pp.833-841
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• 2005

The oxidation resistance and electrical conductivity of various commercial ferritic stainless steels including STS444 were tested in an air atmosphere at $700^{\circ}C$. Crofer22 developed specially for SOFC interconnect was also examined for the aim of comparing with the test results of STS444. Although STS444 exhibited higher oxidation resistance than Corfer22, the electrical conductivity of the scale formed on Crofer22 was higher, indicating that the resistivity of scale formed on Crofer22 is much lower than that of STS444. To gain a better understanding of the relation between oxidation behavior and electrical conductivity, the oxide scales formed on STS444 and Crofer22 were analyzed in terms of the structure, composition, and phase. Consequently, the influence of alloying elements on electrical conductivity of Fe-Cr alloys was discussed.

• 마이크로전자및패키징학회지
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• 제20권3호
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• pp.1-6
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• 2013

TSV는 그동안 3D IC 적층을 하는데 핵심 기술로 많이 연구되어 왔고, RC delay를 줄여 소자의 성능을 향상시키고, 전체 시스템 사이즈를 줄일 수 있는 기술로 각광을 받아왔다. 최근에는 TSV를 전기적 연결이 아닌 소자의 열관리를 위한 구조로 연구되고 있다. TSV를 이용한 liquid cooling 시스템 개발은 TSV 제조, TSV 디자인 (aspect ratio, size, distribution), 배선 밀도, microchannel 제조, sealing, 그리고 micropump 제조까지 풀어야 할 과제가 아직 많이 남아있다. 그러나 TSV를 이용한 liquid cooling 시스템은 열관리뿐 아니라 신호 대기시간(latency), 대역폭(bandwidth), 전력 소비(power consumption), 등에 크게 영향을 미치기 때문에 3D IC 적층 기술의 장점을 최대로 이용한 차세대 cooling 시스템으로 지속적인 개발이 필요하다.

• 한국자동차공학회논문집
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• 제13권6호
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• pp.48-55
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• 2005

In this paper, a mathematical model and a simulation method for the response time analysis of Local Interconnect Network(LIN) based network systems are proposed. Network-induced delays in a network based control system can vary widely according to the transmission time of message and the overhead time of transmission. Therefore, in order to design a distributed control system using LIN network, a method to predict and verify the timing behavior of LIN protocol is required at the network design phase. Furthermore, a simulation environment based on a timing model of LIN protocol is beneficial to predict the timing behavior of LIN. The model equation is formulated with six timing parameters deduced from timing properties of LIN specification. Additionally, LIN conformance test equations to verify LIN device driver are derived with timing constraints of the parameters. The proposed model equation and simulation method are validated with a result that is measured at real LIN based network system.

• Journal of Electrical Engineering and information Science
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• 제2권5호
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.26-28
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• 2005

In this paper, degradation in field-aged PV modules including degradation of interconnect, discoloration of encapsulant and hot spot have been observed and analyzed. From the results, photovoltaic module installed for 15 years shows around 13~20% drop of electrical properties due to the interconnect degradation and PV module passed 19 years has been found to drop of around 20% mainly by the encapsulant discoloration. Fill factor of the electrode oxidized photovoltaic module has been dropped by the amount of 6~10% due to the change of irradiance. It is because maximum voltage(Vmp) decreases according to the increase of irradiance.

• 마이크로전자및패키징학회지
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• 제27권1호
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• pp.45-54
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• 2020

최근 PCB의 소형화, 박형화 및 고밀도화가 크게 요구되면서 MSAP (Modified Semi Additive Process) 기술을 이용한 SLP (Substrate Like PCB) 기술이 큰 주목을 받고 있다. 특히 SLP 기술은 스마트폰의 고용량 배터리 개발과 5G 기술에 꼭 필요한 기술이다. 본 연구에서는 기존의 HDI 기술과 MSAP 기술을 혼합하여 제작한 하이브리드 방식의 SLP의 신뢰성을 실험과 수치해석을 이용하여 분석하였다. 특히 최적의 SLP 설계를 위하여 프리프레그(prepreg)의 물성, 두께, 층수, 마이크로비아(microvia)의 크기 및 misalignment가 마이크로비아의 신뢰성에 미치는 영향을 IST(Interconnect Stress Test) 시험을 이용한 열사이클링 신뢰성 실험과 유한요소 수치해석을 통하여 고찰하였다. SLP 소재인 프리프레그의 열팽창계수가 적을수록 마이크로비아의 신뢰성은 크게 증가하며, 프리프레그의 두께가 얇을수록 신뢰성이 증가된다. 마이크로비아 홀의 크기 및 패드의 크기가 증가하면 응력이 완화되어 신뢰성은 향상된다. 반면 프리프레그의 층수가 증가할수록 마이크로비아의 신뢰성은 감소된다. 또한 misalignment가 크면 신뢰성은 감소하였다. 특히 이들 인자들 중에서 프리프레그의 열팽창계수가 마이크로비아의 신뢰성에 가장 큰 영향을 미친다. 수치 응력해석 결과도 실험 결과와 잘 일치하였으며, 응력이 낮을수록 마이크로비아의 신뢰성은 증가하였다. 본 실험과 수치해석의 결과는 향후 SLP 기판 제작 및 신뢰성 향상을 위한 유용한 설계 가이드라인으로 활용될 것으로 판단된다.

• 한국재료학회지
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• 제20권7호
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• pp.356-363
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• 2010

For this paper, we investigated the area specific resistance (ASR) of commercially available ferritic stainless steels with different chemical compositions for use as solid oxide fuel cells (SOFC) interconnect. After 430h of oxidation, the STS446M alloy demonstrated excellent oxidation resistance and low ASR, of approximately 40 $m{\Omega}cm^2$, of the thermally grown oxide scale, compared to those of other stainless steels. The reason for the low ASR is that the contact resistance between the Pt paste and the oxide scale is reduced due to the plate-like shape of the $Cr_2O_3$(s). However, the acceptable ASR level is considered to be below 100 $m{\Omega}cm^2$ after 40,000 h of use. To further improve the electrical conductivity of the thermally grown oxide on stainless steels, the Co layer was deposited on the stainless steel by means of an electroless deposition method; it was then thermally oxidized to obtain the $Co_3O_4$ layer, which is a highly conductive layer. With the increase of the Co coating thickness, the ASR value decreased. For Co deposited STS444 with 2 ${\mu}m$hickness, the measured ASR at $800^{\circ}$ after 300 h oxidation is around 10 $m{\Omega}cm^2$, which is lower than that of the STS446M, which alloy has a lower ASR value than that of the non-coated STS. The reason for this improved high temperature conductivity seems to be that the Mn is efficiently diffused into the coating layer, which diffusion formed the highly conductive (Mn,Co)$_3O_4$ spinel phases and the thickness of the $Cr_2O_3$(S), which is the rate controlling layer of the electrical conductivity in the SOFC environment and is very thin

• 대한전자공학회논문지SD
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• 제43권10호
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• pp.80-89
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• 2006

급격한 공정 기술의 발전과 새로운 소재의 도입은 공정 제어를 어렵게 할 뿐만 아니라, 공정 편차를 증가시킨다. 이러한 공정 편차는 레이아웃상의 데이타와 실제 웨이퍼 상의 데이타간의 차이를 유발시킴으로써, 설계자가 원하는 성능을 갖는 회로를 구현하는데 많은 장애가 되고 있다. 따라서, 본 논문은 공정 편차가 회로의 특성에 미치는 영향을 $0.13{\mu}m$ 이하의 설계에 반영 할 수 있도록 배선의 worstcase를 정확하고 빠르게 결정할 수 있는 새로운 설계 환경을 구현하였다. 이를 위하여 Common Geometry와 Maximum Probability 기법을 개발하였으며, 이들을 기반으로 새로운 worstcase 최적화 알고리즘을 제안하였다. 본 논문께서 제안된 알고리즘의 정확성 검증은 UMC $0.13{\mu}m$ Logic 공정을 사용하여 제작된 31단 Ring Oscillator의 시간 지연(Delay time)을 측정값과 비교하였다. 검증 결과, 제안된 알고리즘을 사용하여 worstcase 최적화를 할 경우, 신호선 위에 도선이 있는 경우와 없는 경우 모두 상대 오차가 1.0% 내외로 기존의 optimizer를 사용한 경우에 비하여 두배이상 정확함을 알 수 있었다. 또한, 새로운 worstcase 설계 환경을 사용하여 최적화한 경우, 기존의 optimizer를 사용하여 최적화한 경우에 비하여 worstcase 최적화 속도가 약 32.01% 단축되었음을 확인하였다. 더불어, 기존의 방법으로 정확한 시뮬레이션이 어려웠던 비정규분포를 갖는 경우에 대해서도 정확한 worstcase를 예측함을 확인하였다.