• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.293-304
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• 2011

In this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixIII EP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.

• The KIPS Transactions:PartB
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• v.10B no.5
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• pp.553-560
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• 2003

Since Wavelet Transform decomposes a video frame into subbands with various frequencies and resolutions, the reconstructed video qualify at a receiver fluctuates according to the location of transmission errors within frames. This deteriorates the whole visual duality of the video. Specifically, for a wavelet based video which exploits the motion estimation prediction scheme, the transmission errors of a subband not only have a bad effect on other subbands within a same frame but also propagates to the subsequent frames. In this paper, we propose BDP(Block Based Dispersive Packetization) scheme, for a wavelet based video stream, which maintains constant video quality despite packet location that a transmission error occurs. To evaluate the performance of the proposed scheme, we use MRME(Multi-Resolution Motion Estimation) scheme to compress a video in Inter coding mode and Gilbert´s error model to generate the error patterns in wireless network environment. The simulation results show that BDP is more efficient than BP (Block based Packetization) or DP (Dispersive Packetization) in both PSNR and visual quality.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1377-1383
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• 2012

The first frame of a GOP is encoded in intra mode which generates a larger number of bits. In addition, the first frame is used for the inter mode encoding of the following frames. Thus the intial QP for the first frame affects the first frame as well as the following frames. Traditionally, the initial QP is determined among four constant values only depending on the bpp. Although this initialization scheme is simple, yet it is not accurate enough. An accurate intial QP prediction scheme should not only depends on bpp but also on the complexity of the video sequence and the output bandwidth. In this paper, we propose a traffic model for finding the optimal initial QP which maximizes the PSNR of the GOP. We also propose a method to find model parameters for real-time video encoding. It is shown by experimental results that the proposed traffic model captures initial QP characteristics effectively and the proposed method for model parameters accurately estimates the real values.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.9
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• pp.1325-1332
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• 2013

The first frame of a GOP, an I frame, is encoded in intra mode which generates a larger number of bits. In addition, the I frame is used for the inter mode encoding of the following frames. Thus the intial QP for the I frame affects the first frame as well as the following frames. In our previous work, we analyzed the number of bits for an I frame and showed that the ratio of the number of bits which maximizes the PSNR of a GOP maintains similar value regardless of GOP's. In this paper, we propose a R-Q model which can be used for the calculation of the initial QP given the amount of bits for an I frame. The proposed model is simple and adaptively modifies model parameters, so it can be applicable to the real-time application. It is shown by experimental results that the proposed model captures initial QP characteristics effectively and the proposed method for model parameters accurately estimates the real values.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1541-1550
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• 2004

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2071-2078
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• 2009

The first frame is encoded in intra mode which generates a larger number of bits. In addition, the first frame is used for the inter mode encoding of the following frames. Thus the intial QP (Quantization Parameter) for the first frame affects the first frame as well as the following frames. Traditionally, the initial QP is determined among four constant values only depending on the bpp. In the case of low bit rate video coding, the initial QP value is fixed to 35 regardless of the output bandwidth. Although this initialization scheme is simple, yet it is not accurate enough. An accurate intial QP prediction scheme should not only depends on bpp but also on the complexity of the video sequence and the output bandwidth. In the proposed scheme, we use a linear model because there is a linear inverse proportional relationship between the output bandwidth and the optimal intial QP. Model parameters of the model are determined depending on the spatial complexity of the first frame. It is shown by experimental results that the new algorithm can predict the optimal initial QP more accurately and generate the PSNR performance better than that of the existing JM algorithm.

• Earthquakes and Structures
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• v.21 no.5
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• pp.515-530
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• 2021

In a tall reinforced concrete (RC) core wall system subjected to strong ground motions, inelastic behavior near the base as well as mid-height of the wall is possible. Generally, the formation of plastic hinge in a core wall system may lead to extensive damage and significant repairing cost. A new configuration of core structures consisting of buckling restrained braced frames (BRBFs) and RC walls is an interesting idea in tall building seismic design. This concept can be used in the plan configuration of tall core wall systems. In this study, tall buildings with different configurations of combined core systems were designed and analyzed. Nonlinear time history analysis at severe earthquake level was performed and the results were compared for different configurations. The results demonstrate that using enough BRBFs can reduce the large curvature ductility demand at the base and mid-height of RC core wall systems and also can reduce the maximum inter-story drift ratio. For a better investigation of the structural behavior, the probabilistic approach can lead to in-depth insight. Therefore, incremental dynamic analysis (IDA) curves were calculated to assess the performance. Fragility curves at different limit states were then extracted and compared. Mean IDA curves demonstrate better behavior for a combined system, compared with conventional RC core wall systems. Collapse margin ratio for a RC core wall only system and RC core with enough BRBFs were almost 1.05 and 1.92 respectively. Therefore, it appears that using one RC core wall combined with enough BRBF core is an effective idea to achieve more confidence against tall building collapse and the results demonstrated the potential of the proposed system.

• Structural Engineering and Mechanics
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• v.90 no.3
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• pp.313-323
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• 2024

Most of existing buildings in Mexico City are made of reinforced concrete (RC), however, it has been shown that they are very susceptible to narrow-band long duration ground motions. In recent years, the use of dual systems composed by Buckling Restrained Braces (BRB) has increased due to its high energy dissipation capacity under reversible cyclical loads. Therefore, in this work the behavior of RC buildings with BRB is studied in order to know their performance, specifically, the energy distribution through height and response transformation factors between the RC and simplified systems are estimated. For this propose, seven RC buildings with different heights were designed according to the Mexico City Seismic Design Provisions (MCSDP), in addition, equivalent single degree of freedom (SDOF) systems were obtained. Incremental dynamic analyses on the buildings under 30 narrow-band ground motions in order to compute the relationship between normalized hysteretic energy, maximum inter-story drift and roof displacement demands were performed. The results shown that the entire structural frames participate in energy dissipation and their distribution is independent of the global ductility. The results let propose energy distribution equations through height. Finally, response transformation factors between the SDOF and multi degree of freedom (MDOF) systems were developed aimed to propose a new energy-based approach of BRB reinforced concrete buildings.

• Journal of Broadcast Engineering
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• v.12 no.6
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• pp.611-623
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• 2007

The H.264|AVC standard incorporates an intra prediction tool into inter frame coding. However, this leads to excessive amount of increase in encoding time, thus resulting in the difficulty in real-time implementation of software encoders. In this paper, we first propose an early decision on intra prediction coding and a fast intra prediction method using the characteristics of block contents and the context of neighboring block modes for the intra prediction in the inter frame coding of H.264/AVC. Basically, the proposed methods determine a skip condition on whether the $4{\times}4$ intra prediction is to be used in the inter frame coding by considering the content characteristics of each block to be encoded and the context of its neighboring blocks. The performance of our proposed methods is compared with the Joint Model reference software version 11.0 of H.264|AVC. The experimental results show that our proposed methods allow for 41.63% reduction in the total encoding time with negligible amounts of PSNR drops and bitrate increases, compared to the original Joint Model reference software version 11.0.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.446-457
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• 2017

In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.