• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.365-368
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• 1999

In this paper, we investigate the effect of adopting branch-penalty compensation schemes on the power performance of TLBs(Translation Look-aside Buffers) and instruction caches. We found that the double-buffer branch-penalty compensation scheme can reduce the power consumption of the TLBs and the instruction caches considered by up to 14-21.3%. The power consumption is estimated through simulation at the architectural level, using the Kamble/Ghose method

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1995.10b
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• pp.139-144
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• 1995

LIBL(Linguistic Instruction Based Leaning) is an effective learning algorithm for fuzzy controller which interpretes and uses natural language of human The possibiliy of the LIBL algorithm to the fuzzy control of dynamic systems is investigated in this paper. Rise time, percent overshoot, and steady stste are proposed as suitable meaning elements for dynamic systems. A supervisor is able to give "higer-level linguistic instruction" to the learning algorithm through these three meaning elements Simulation results for a DC servo motor show the validity of the proposed algorithm.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1201-1210
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• 1990

This paper proposes on-chip instruction and data cache memories on RISC reduced instruction set computer) architecture which supports fast instruction fetch and data read/write, and enables RISC processor under research to obtain high performance. In the execution of HLL(high level language) programs, heavily used local scalar variables are stored in large register file, but arrays, structures, and global scalar variables are difficult for compiler to allocate registers. These problems can be solved by on-chip Instruction/Data cache. And each cycle of instruction fetch, pad delay causes the lowering of the processors's performance. Cache memories are designed in CMOS technology and SRAM(static-RAM), that saves layout area and power dissipation, is used for instruction and data storage. To speed up and support RISC processor's piplined architecture efficiently, hardwired logic technology is used overall circuits i cache blocks. The schematic capture and timing simulation of proposed cache memorises are performed on Apollo DN4000 workstation using Mentor Graphics CAD tools.

• Journal of the Korea Society of Computer and Information
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• v.10 no.2 s.34
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• pp.87-95
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• 2005

value prediction in high performance micro processors is a technique that exploits Instruction Level Parallelism(ILP) by predicting the outcome of an instruction and by breaking and executing true data dependences. In this paper, the mean Performance improvements by predictor according to a point of time for update of each table as well as prediction accuracy and Prediction rate are measured and assessed by comparison and analysis of value predictor that issues in parallel and run by predicting value, which is for Performance improvements of ILP in micro Processor. For the verification of its validity the SPECint95 benchmark through the simulation is compared by making use of execution driven system.

• Journal of the Korea Society of Computer and Information
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• v.14 no.12
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• pp.9-16
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• 2009

Energy consumption as well as performance should be considered when designing up-to-date multicore processors. In this paper, we propose new design technique to reduce the energy consumption in the instruction cache for multicore processors by using modified filter cache. The filter cache has been recognized as one of the most energy-efficient design techniques for singlecore processors. The energy consumed in the instruction cache accounts for a significant portion of total processor energy consumption. Therefore, energy-aware instruction cache design techniques are essential to reduce the energy consumption in a multicore processor. The proposed technique reduces the energy consumption in the instruction cache for multicore processors by reducing the number of accesses to the level-1 instruction cache. We evaluate the proposed design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed architecture reduces the energy consumption in the instruction cache for multicore processors by up to 3.4% compared to the conventional filter cache architecture. Moreover, the proposed architecture shows better performance over the conventional filter cache architecture.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.7
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• pp.3152-3159
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• 2012

This paper presents the new instruction-level power model for an asynchronous processor. Until now, the various power models for estimating the power dissipation of embedded processor in SoC are proposed. Since all of them are target to the synchronous processors, the accuracy is questionable when we apply those power models to the asynchronous processor in SoC. To solve this problem, we present new power model for an asynchronous processor by reflecting the behavioral features of an asynchronous circuit. The proposed power model is verified using an implementation of asynchronous processor, A8051. The simulation results of the proposed model is compared with the measurement result of gate-level synthesized A8051. The proposed power model shows the accuracy of 90.7% and the simulation time for estimation the power consumption was reduced to 1,900 times.

• The Journal of Korean Academic Society of Nursing Education
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• v.21 no.1
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• pp.86-94
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• 2015

Purpose: The purpose of this study was to compare practice stress and practice satisfaction between clinical practice and simulation-based practice groups. Methods: A total of 159 nursing students (85 in the simulation group and 74 in the NICU group) participated in the study. Research tools measuring practice stress and practice satisfaction were used. Data was analyzed utilizing a t-test, Mann Whitney U-test, and descriptive statistics. Results: The simulation group showed a lower level of practice stress(practice instruction, practice evaluation, interpersonal relationship) a higher level of practice satisfaction compared with the NICU group. Conclusion: Simulation-based practice is an effective learning method for high-risk newborn nursing and can be used as an alternative to clinical practice.

• Proceedings of the Korea Society for Simulation Conference
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• 2005.11a
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• pp.108-112
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• 2005

유비쿼터스 컴퓨팅의 기반 설비인 센서 네트워크는 많은 수의 센서 노드들로 구성되며, 각 센서 노드의 하드웨어는 매우 작은 규모이다. 또한 센서 네트워크는 구축 목적에 따라 네트워크 토폴로지 및 라우팅 방식이 결정되어야 하고, 이와 더불어 센서 노드의 하드웨어와 소프트웨어도 필요에 따라 다양하게 변경되어야 한다. 따라서 센서 네트워크가 구현되기 전에 시스템 동작과 성능을 예측할 수 있는 센서 네트워크 시뮬레이터가 필요하다. 기존의 센서 네트워크 시뮬레이터들은 특별한 응용을 위한 특정 기반의 하드웨어와 운영체제에 국한되어 개발되었기 때문에 다양한 센서 네트워크 환경을 지원하기에는 한계가 있으며, 센서 네트워크 설계상의 주요 요소인 전력소모량과 실행 시간에 대한 분석이 포함되지 않았다. 따라서 본 연구에서는 특정한 응용이나 운영체제에 제한을 받지 않으면서 다양하게 센서 네트워크 환경을 설계 및 검증할 수 있고, 더불어 전력소모량과 실행시간 추정도 가능한 시뮬레이터를 개발하는 것을 목표로 하였다. 이를 위해 본 연구에서 개발한 시뮬레이터는 기계명령어-레벨(machine instruction-level)의 이산-사건 시뮬레이션(discrete-event simulation) 기법을 이용함으로써 실제 센서 노드의 프로그램 실행 및 관련 동작들을 세부적으로 예측하는 데 사용될 수 있도록 하였다. 시뮬레이션의 작업부하(workload)인 명령어 트레이스(instruction trace)로는 ATmega128L 마이크로컨트롤러용으로 크로스 컴파일된 인텔 핵스-레코드(.hex) 형식을 사용한다.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9B
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• pp.939-946
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• 2009

In this paper, we propose a new network ASIP(Application Specific Instruction-set Processor) which was designed for simulation models by a machine descriptions language LISA(Language for Instruction Set Architecture). This network ASIP is aimed for an exclusive engine undertaking packet processing in a router. To achieve the purpose, we added a new necessary instruction set for processing a general ASIP based on MIPS(Microprocessor without Interlock Pipeline Stages) architecture in high speed. The new instructions can be divided into two groups: a classification instruction group and a modification instruction group, and each group is to be processed by its own functional unit in an execution stage. The functional unit was optimized for area and speed through Verilog HDL, and the result after synthesis was compared with the area and operation delay time. Moreownr, it was allocated to the Macro function ana low-level standardized programming language C using CKF(Compiler Known Function). Consequently, we verified performance improvement achieved by analysis and comparison of execution cycles of application programs.